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rocket-chip/csrc/emulator.cc

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#include "htif_emulator.h"
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#include "common.h"
#include "emulator.h"
#include "mm.h"
#include "mm_dramsim2.h"
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#include "disasm.h"
#include "Top.h" // chisel-generated code...
#include <fcntl.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
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#include <unistd.h>
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htif_emulator_t* htif;
void handle_sigterm(int sig)
{
htif->stop();
}
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int main(int argc, char** argv)
{
unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
uint64_t max_cycles = 0;
uint64_t trace_count = 0;
int start = 0;
const char* vcd = NULL;
const char* loadmem = NULL;
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FILE *vcdfile = NULL;
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const char* failure = NULL;
disassembler disasm;
bool dramsim2 = false;
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bool log = false;
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for (int i = 1; i < argc; i++)
{
std::string arg = argv[i];
if (arg.substr(0, 2) == "-v")
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vcd = argv[i]+2;
else if (arg.substr(0, 2) == "-s")
random_seed = atoi(argv[i]+2);
else if (arg == "+dramsim")
dramsim2 = true;
else if (arg == "+verbose")
log = true;
else if (arg.substr(0, 12) == "+max-cycles=")
max_cycles = atoll(argv[i]+12);
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else if (arg.substr(0, 9) == "+loadmem=")
loadmem = argv[i]+9;
}
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const int disasm_len = 24;
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if (vcd)
{
// Create a VCD file
vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
assert(vcdfile);
fprintf(vcdfile, "$scope module Testbench $end\n");
fprintf(vcdfile, "$var reg %d NDISASM_WB wb_instruction $end\n", disasm_len*8);
fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
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fprintf(vcdfile, "$upscope $end\n");
}
// The chisel generated code
Top_t tile;
srand(random_seed);
tile.init(random_seed != 0);
// Instantiate and initialize main memory
mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
mm->init(MEM_SIZE, tile.Top__io_mem_resp_bits_data.width()/8, LINE_SIZE);
if (loadmem)
load_mem(mm->get_data(), loadmem);
// Instantiate HTIF
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htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
int htif_bits = tile.Top__io_host_in_bits.width();
assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits());
signal(SIGTERM, handle_sigterm);
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// reset for a few cycles to support pipelined reset
tile.Top__io_host_in_valid = LIT<1>(0);
tile.Top__io_host_out_ready = LIT<1>(0);
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tile.Top__io_mem_backup_en = LIT<1>(0);
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for (int i = 0; i < 10; i++)
{
tile.clock_lo(LIT<1>(1));
tile.clock_hi(LIT<1>(1));
}
while (!htif->done())
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{
tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
tile.clock_lo(LIT<1>(0));
mm->tick(
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tile.Top__io_mem_req_cmd_valid.lo_word(),
tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
tile.Top__io_mem_req_data_valid.lo_word(),
&tile.Top__io_mem_req_data_bits_data.values[0],
tile.Top__io_mem_resp_ready.to_bool()
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);
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if (tile.Top__io_host_clk_edge.to_bool())
{
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static bool htif_in_valid = false;
static val_t htif_in_bits;
if (tile.Top__io_host_in_ready.to_bool() || !htif_in_valid)
htif_in_valid = htif->recv_nonblocking(&htif_in_bits, htif_bits/8);
tile.Top__io_host_in_valid = LIT<1>(htif_in_valid);
tile.Top__io_host_in_bits = LIT<64>(htif_in_bits);
if (tile.Top__io_host_out_valid.to_bool())
htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8);
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tile.Top__io_host_out_ready = LIT<1>(1);
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}
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if (tile.Top__io_debug_error_mode.lo_word())
{
failure = "entered error mode";
break;
}
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if (log)
tile.print(stderr);
if (vcd)
tile.dump(vcdfile, trace_count);
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tile.clock_hi(LIT<1>(0));
trace_count++;
if (max_cycles != 0 && trace_count == max_cycles)
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{
failure = "timeout";
break;
}
}
if (vcd)
fclose(vcdfile);
delete htif;
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if (failure)
{
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fprintf(stderr, "*** FAILED *** (%s) after %lld cycles\n", failure, (long long)trace_count);
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return -1;
}
return 0;
}