2012-10-11 00:42:39 +02:00
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package uncore
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2012-03-26 02:03:58 +02:00
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import Chisel._
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import scala.math._
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2013-08-12 19:36:44 +02:00
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trait HasMemData extends Bundle {
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2013-08-02 23:55:06 +02:00
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val data = Bits(width = MEM_DATA_BITS)
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}
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2013-08-12 19:36:44 +02:00
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trait HasMemAddr extends Bundle {
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val addr = UInt(width = MEM_ADDR_BITS)
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2013-08-02 23:55:06 +02:00
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}
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2013-08-12 19:36:44 +02:00
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trait HasMemTag extends Bundle {
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val tag = UInt(width = MEM_TAG_BITS)
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2013-08-02 23:55:06 +02:00
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}
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2013-08-12 19:36:44 +02:00
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class MemReqCmd extends HasMemAddr with HasMemTag {
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val rw = Bool()
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}
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class MemResp extends HasMemData with HasMemTag
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class MemData extends HasMemData
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2013-08-02 23:55:06 +02:00
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class ioMem extends Bundle {
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2013-08-12 19:36:44 +02:00
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val req_cmd = Decoupled(new MemReqCmd)
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val req_data = Decoupled(new MemData)
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val resp = Decoupled(new MemResp).flip
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2013-08-02 23:55:06 +02:00
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}
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class ioMemPipe extends Bundle {
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2013-08-12 19:36:44 +02:00
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val req_cmd = Decoupled(new MemReqCmd)
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val req_data = Decoupled(new MemData)
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val resp = Valid(new MemResp).flip
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2013-08-02 23:55:06 +02:00
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}
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2012-10-19 01:56:36 +02:00
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class ioMemSerialized(w: Int) extends Bundle
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2012-03-26 02:03:58 +02:00
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{
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2013-08-12 19:36:44 +02:00
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val req = Decoupled(Bits(width = w))
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val resp = Valid(Bits(width = w)).flip
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2012-03-26 02:03:58 +02:00
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}
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2013-08-12 19:36:44 +02:00
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class MemSerdes(w: Int) extends Module
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2012-03-26 02:03:58 +02:00
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{
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val io = new Bundle {
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val wide = new ioMem().flip
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2012-10-19 01:56:36 +02:00
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val narrow = new ioMemSerialized(w)
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2012-03-26 02:03:58 +02:00
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}
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val abits = io.wide.req_cmd.bits.toBits.getWidth
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val dbits = io.wide.req_data.bits.toBits.getWidth
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val rbits = io.wide.resp.bits.getWidth
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2013-08-12 19:36:44 +02:00
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val out_buf = Reg(Bits())
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val in_buf = Reg(Bits())
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2012-03-26 02:03:58 +02:00
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2013-09-10 19:54:51 +02:00
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val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(UInt(), 5)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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val send_cnt = Reg(init=UInt(0, log2Up((max(abits, dbits)+w-1)/w)))
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val data_send_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES)))
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2013-08-12 19:36:44 +02:00
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val adone = io.narrow.req.ready && send_cnt === UInt((abits-1)/w)
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val ddone = io.narrow.req.ready && send_cnt === UInt((dbits-1)/w)
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2012-03-26 02:03:58 +02:00
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2012-03-26 08:03:20 +02:00
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when (io.narrow.req.valid && io.narrow.req.ready) {
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2013-08-12 19:36:44 +02:00
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send_cnt := send_cnt + UInt(1)
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out_buf := out_buf >> UInt(w)
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2012-03-26 08:03:20 +02:00
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}
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when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
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out_buf := io.wide.req_cmd.bits.toBits
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}
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when (io.wide.req_data.valid && io.wide.req_data.ready) {
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out_buf := io.wide.req_data.bits.toBits
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}
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io.wide.req_cmd.ready := state === s_idle
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io.wide.req_data.ready := state === s_write_idle
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io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
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io.narrow.req.bits := out_buf
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when (state === s_idle && io.wide.req_cmd.valid) {
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state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
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2012-03-26 02:03:58 +02:00
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}
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when (state === s_read_addr && adone) {
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state := s_idle
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2013-08-12 19:36:44 +02:00
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send_cnt := UInt(0)
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2012-03-26 02:03:58 +02:00
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}
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when (state === s_write_addr && adone) {
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state := s_write_idle
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2013-08-12 19:36:44 +02:00
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send_cnt := UInt(0)
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2012-03-26 02:03:58 +02:00
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}
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when (state === s_write_idle && io.wide.req_data.valid) {
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state := s_write_data
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}
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when (state === s_write_data && ddone) {
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2013-08-12 19:36:44 +02:00
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data_send_cnt := data_send_cnt + UInt(1)
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state := Mux(data_send_cnt === UInt(REFILL_CYCLES-1), s_idle, s_write_idle)
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send_cnt := UInt(0)
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2012-03-26 02:03:58 +02:00
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}
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2013-08-16 00:27:38 +02:00
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val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
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val data_recv_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES)))
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val resp_val = Reg(init=Bool(false))
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2012-03-26 02:03:58 +02:00
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resp_val := Bool(false)
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when (io.narrow.resp.valid) {
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2013-08-12 19:36:44 +02:00
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recv_cnt := recv_cnt + UInt(1)
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when (recv_cnt === UInt((rbits-1)/w)) {
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recv_cnt := UInt(0)
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data_recv_cnt := data_recv_cnt + UInt(1)
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2012-03-26 02:03:58 +02:00
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resp_val := Bool(true)
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}
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2012-10-19 01:56:36 +02:00
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in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+w-1)/w*w-1,w))
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2012-03-26 02:03:58 +02:00
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}
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io.wide.resp.valid := resp_val
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2013-08-25 00:24:17 +02:00
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io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
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2012-03-26 02:03:58 +02:00
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}
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2012-03-26 08:03:20 +02:00
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2012-10-19 01:56:36 +02:00
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class MemDesserIO(w: Int) extends Bundle {
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val narrow = new ioMemSerialized(w).flip
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val wide = new ioMem
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}
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2013-08-12 19:36:44 +02:00
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class MemDesser(w: Int) extends Module // test rig side
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2012-03-26 08:03:20 +02:00
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{
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2012-10-19 01:56:36 +02:00
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val io = new MemDesserIO(w)
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2012-03-26 08:03:20 +02:00
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val abits = io.wide.req_cmd.bits.toBits.getWidth
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val dbits = io.wide.req_data.bits.toBits.getWidth
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val rbits = io.wide.resp.bits.getWidth
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require(dbits >= abits && rbits >= dbits)
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2013-08-16 00:27:38 +02:00
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val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w)))
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val data_recv_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES)))
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2013-08-12 19:36:44 +02:00
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val adone = io.narrow.req.valid && recv_cnt === UInt((abits-1)/w)
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val ddone = io.narrow.req.valid && recv_cnt === UInt((dbits-1)/w)
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val rdone = io.narrow.resp.valid && recv_cnt === UInt((rbits-1)/w)
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2012-03-26 08:03:20 +02:00
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2013-09-10 19:54:51 +02:00
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val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(UInt(), 5)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_cmd_recv)
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2012-03-26 08:03:20 +02:00
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2013-08-12 19:36:44 +02:00
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val in_buf = Reg(Bits())
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2012-03-26 08:03:20 +02:00
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when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) {
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2013-08-12 19:36:44 +02:00
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recv_cnt := recv_cnt + UInt(1)
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2012-10-19 01:56:36 +02:00
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in_buf := Cat(io.narrow.req.bits, in_buf((rbits+w-1)/w*w-1,w))
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2012-03-26 08:03:20 +02:00
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}
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io.narrow.req.ready := state === s_cmd_recv || state === s_data_recv
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when (state === s_cmd_recv && adone) {
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state := s_cmd
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2013-08-12 19:36:44 +02:00
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recv_cnt := UInt(0)
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2012-03-26 08:03:20 +02:00
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}
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when (state === s_cmd && io.wide.req_cmd.ready) {
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state := Mux(io.wide.req_cmd.bits.rw, s_data_recv, s_reply)
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}
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when (state === s_data_recv && ddone) {
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state := s_data
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2013-08-12 19:36:44 +02:00
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recv_cnt := UInt(0)
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2012-03-26 08:03:20 +02:00
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}
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when (state === s_data && io.wide.req_data.ready) {
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state := s_data_recv
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2013-08-12 19:36:44 +02:00
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when (data_recv_cnt === UInt(REFILL_CYCLES-1)) {
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2012-03-26 08:03:20 +02:00
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state := s_cmd_recv
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}
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2013-08-12 19:36:44 +02:00
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data_recv_cnt := data_recv_cnt + UInt(1)
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2012-03-26 08:03:20 +02:00
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}
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when (rdone) { // state === s_reply
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2013-08-12 19:36:44 +02:00
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when (data_recv_cnt === UInt(REFILL_CYCLES-1)) {
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2012-03-26 08:03:20 +02:00
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state := s_cmd_recv
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}
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2013-08-12 19:36:44 +02:00
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recv_cnt := UInt(0)
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data_recv_cnt := data_recv_cnt + UInt(1)
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2012-03-26 08:03:20 +02:00
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}
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2013-08-12 19:36:44 +02:00
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val req_cmd = in_buf >> UInt(((rbits+w-1)/w - (abits+w-1)/w)*w)
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2012-03-26 08:03:20 +02:00
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io.wide.req_cmd.valid := state === s_cmd
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2012-10-11 00:42:39 +02:00
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io.wide.req_cmd.bits := io.wide.req_cmd.bits.fromBits(req_cmd)
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2012-03-26 08:03:20 +02:00
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io.wide.req_data.valid := state === s_data
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2013-08-12 19:36:44 +02:00
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io.wide.req_data.bits.data := in_buf >> UInt(((rbits+w-1)/w - (dbits+w-1)/w)*w)
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2012-03-26 08:03:20 +02:00
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2013-08-12 19:36:44 +02:00
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val dataq = Module(new Queue(new MemResp, REFILL_CYCLES))
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2012-03-26 08:03:20 +02:00
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dataq.io.enq <> io.wide.resp
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2013-08-12 19:36:44 +02:00
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dataq.io.deq.ready := recv_cnt === UInt((rbits-1)/w)
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2012-03-26 08:03:20 +02:00
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io.narrow.resp.valid := dataq.io.deq.valid
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2013-08-12 19:36:44 +02:00
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io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UInt(w))
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2012-03-26 08:03:20 +02:00
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}
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