2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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2016-05-10 09:25:13 +02:00
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2016-06-28 20:21:38 +02:00
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package uncore.devices
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2016-05-10 09:25:13 +02:00
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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2016-10-29 06:20:49 +02:00
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import diplomacy._
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2016-10-26 22:52:23 +02:00
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import regmapper._
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import uncore.tilelink2._
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2016-11-18 23:05:14 +01:00
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import config._
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2016-10-29 06:20:49 +02:00
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import scala.math.min
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2016-05-10 09:25:13 +02:00
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class GatewayPLICIO extends Bundle {
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val valid = Bool(OUTPUT)
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val ready = Bool(INPUT)
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val complete = Bool(INPUT)
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}
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class LevelGateway extends Module {
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val io = new Bundle {
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val interrupt = Bool(INPUT)
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val plic = new GatewayPLICIO
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}
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val inFlight = Reg(init=Bool(false))
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when (io.interrupt && io.plic.ready) { inFlight := true }
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when (io.plic.complete) { inFlight := false }
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io.plic.valid := io.interrupt && !inFlight
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}
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2016-10-27 22:09:11 +02:00
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object PLICConsts
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{
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2016-05-10 09:25:13 +02:00
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def maxDevices = 1023
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2016-06-06 05:33:51 +02:00
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def maxHarts = 15872
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2016-10-26 22:52:23 +02:00
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def priorityBase = 0x0
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2016-06-06 05:33:51 +02:00
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def pendingBase = 0x1000
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def enableBase = 0x2000
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def hartBase = 0x200000
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def claimOffset = 4
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def priorityBytes = 4
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2016-05-10 09:25:13 +02:00
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2016-10-27 22:09:11 +02:00
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def enableOffset(i: Int) = i * ((maxDevices+7)/8)
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def hartOffset(i: Int) = i * 0x1000
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def enableBase(i: Int):Int = enableOffset(i) + enableBase
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def hartBase(i: Int):Int = hartOffset(i) + hartBase
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def size = hartBase(maxHarts)
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require(hartBase >= enableBase(maxHarts))
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}
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2016-10-29 06:20:49 +02:00
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/** Platform-Level Interrupt Controller */
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2016-12-02 02:46:52 +01:00
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class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
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{
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val contextsPerHart = if (supervisor) 2 else 1
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require (maxPriorities >= 0)
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val node = TLRegisterNode(
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address = AddressSet(address, PLICConsts.size-1),
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beatBytes = p(rocket.XLen)/8,
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undefZero = false)
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val intnode = IntAdapterNode(
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numSourcePorts = 0 to 1024,
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numSinkPorts = 0 to 1024,
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(contextsPerHart))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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2016-11-22 23:58:03 +01:00
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/* Negotiated sizes */
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def nDevices = intnode.edgesIn.map(_.source.num).sum
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def nPriorities = min(maxPriorities, nDevices)
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def nHarts = intnode.edgesOut.map(_.source.num).sum
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
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def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
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def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
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// Create the global PLIC config string
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lazy val globalConfigString = Seq(
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s"plic {\n",
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s" priority 0x${address.toString(16)};\n",
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s" pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
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s" ndevs ${nDevices};\n",
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s"};\n").mkString
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// Create the per-Hart config string
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lazy val hartConfigStrings = Seq.tabulate(intnode.edgesOut.size) { i => (Seq(
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s" plic {\n",
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s" m {\n",
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s" ie 0x${enableAddr(i, 'M').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'M').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'M').toString(16)};\n",
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s" };\n") ++ (if (!supervisor) Seq() else Seq(
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s" s {\n",
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s" ie 0x${enableAddr(i, 'S').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'S').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'S').toString(16)};\n",
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s" };\n")) ++ Seq(
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s" };\n")).mkString
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}
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2016-10-29 06:20:49 +02:00
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val tl_in = node.bundleIn
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val devices = intnode.bundleIn
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val harts = intnode.bundleOut
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}
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// Assign all the devices unique ranges
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val sources = intnode.edgesIn.map(_.source)
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val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten
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// Compact the interrupt vector the same way
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val interrupts = (intnode.edgesIn zip io.devices).map { case (e, i) => i.take(e.source.num) }.flatten
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// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
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val harts = io.harts.flatten
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println("\nInterrupt map:")
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flatSources.foreach { s =>
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2016-10-29 21:39:04 +02:00
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// +1 because 0 is reserved, +1-1 because the range is half-open
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println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
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}
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2016-11-22 23:58:03 +01:00
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require (nDevices == interrupts.size)
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require (nHarts == harts.size)
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require(nDevices <= PLICConsts.maxDevices)
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require(nHarts > 0 && nHarts <= PLICConsts.maxHarts)
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// For now, use LevelGateways for all TL2 interrupts
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val gateways = Vec(interrupts.map { case i =>
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := i
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gateway.io.plic
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2016-11-19 03:07:44 +01:00
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} ++ (if (interrupts.isEmpty) Some(Wire(new GatewayPLICIO)) else None))
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2016-10-29 06:20:49 +02:00
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val priority =
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if (nPriorities > 0) Reg(Vec(nDevices+1, UInt(width=log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nDevices+1)(UInt(1)))
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val threshold =
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if (nPriorities > 0) Reg(Vec(nHarts, UInt(width = log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nHarts)(UInt(0)))
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val pending = Reg(init=Vec.fill(nDevices+1){Bool(false)})
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val enables = Reg(Vec(nHarts, Vec(nDevices+1, Bool())))
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for ((p, g) <- pending.tail zip gateways) {
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g.ready := !p
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g.complete := false
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when (g.valid) { p := true }
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}
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def findMax(x: Seq[UInt]): (UInt, UInt) = {
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if (x.length > 1) {
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val half = 1 << (log2Ceil(x.length) - 1)
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val lMax = findMax(x take half)
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val rMax = findMax(x drop half)
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val useLeft = lMax._1 >= rMax._1
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) | rMax._2))
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} else (x.head, UInt(0))
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}
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val maxDevs = Reg(Vec(nHarts, UInt(width = log2Up(pending.size))))
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for (hart <- 0 until nHarts) {
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val effectivePriority =
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for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail)
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yield Cat(p && en, pri)
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val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority)
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maxDevs(hart) := maxDev
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harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart))
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}
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def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
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}
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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PLICConsts.hartBase(i) -> Seq(
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priorityRegField(threshold(i)),
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RegField(32,
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RegReadFn { valid =>
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when (valid) {
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pending(maxDevs(i)) := Bool(false)
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maxDevs(i) := UInt(0) // flush pipeline
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}
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(Bool(true), maxDevs(i))
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},
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RegWriteFn { (valid, data) =>
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when (valid && enables(i)(data)) {
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gateways(data - UInt(1)).complete := Bool(true)
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}
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Bool(true)
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2016-10-26 22:52:23 +02:00
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}
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2016-10-29 06:20:49 +02:00
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)
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2016-10-26 22:52:23 +02:00
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)
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2016-10-29 06:20:49 +02:00
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}
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2016-05-10 09:25:13 +02:00
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2016-10-29 06:20:49 +02:00
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node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
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2016-10-26 22:52:23 +02:00
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2016-10-29 06:20:49 +02:00
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priority(0) := 0
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pending(0) := false
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for (e <- enables)
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e(0) := false
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}
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2016-05-10 09:25:13 +02:00
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}
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