2016-05-10 09:25:13 +02:00
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// See LICENSE for license details.
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package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import cde.Parameters
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class GatewayPLICIO extends Bundle {
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val valid = Bool(OUTPUT)
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val ready = Bool(INPUT)
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val complete = Bool(INPUT)
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}
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class LevelGateway extends Module {
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val io = new Bundle {
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val interrupt = Bool(INPUT)
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val plic = new GatewayPLICIO
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}
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val inFlight = Reg(init=Bool(false))
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when (io.interrupt && io.plic.ready) { inFlight := true }
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when (io.plic.complete) { inFlight := false }
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io.plic.valid := io.interrupt && !inFlight
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}
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int) {
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def contextsPerHart = if (supervisor) 2 else 1
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def nHarts = contextsPerHart * nHartsIn
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = hartBase + hartOffset(context(i, mode)) + claimOffset
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def threshAddr(i: Int, mode: Char) = hartBase + hartOffset(context(i, mode))
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def enableAddr(i: Int, mode: Char) = enableBase + enableOffset(context(i, mode))
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def size = hartBase + hartOffset(maxHarts)
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def maxDevices = 1023
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def maxHarts = 992
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def pendingBase = 0x800
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def enableBase = 0x1000
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def enableOffset(i: Int) = i * ((maxDevices+7)/8)
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def hartBase = enableBase + enableOffset(maxHarts)
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def hartOffset(i: Int) = i * 0x1000
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def claimOffset = 2
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require(nDevices > 0 && nDevices <= maxDevices)
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require(nHarts > 0 && nHarts <= maxHarts)
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2016-06-02 22:48:29 +02:00
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require(nPriorities >= 0 && nPriorities <= nDevices)
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2016-05-10 09:25:13 +02:00
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}
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/** Platform-Level Interrupt Controller */
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class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val devices = Vec(cfg.nDevices, new GatewayPLICIO).flip
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val harts = Vec(cfg.nHarts, Bool()).asOutput
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val tl = new ClientUncachedTileLinkIO().flip
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}
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2016-06-02 22:48:29 +02:00
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val priority =
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if (cfg.nPriorities > 0) Reg(Vec(cfg.nDevices+1, UInt(width=log2Up(cfg.nPriorities+1))))
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else Wire(init=Vec.fill(cfg.nDevices+1)(UInt(1)))
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2016-05-10 09:25:13 +02:00
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val pending = Reg(init=Vec.fill(cfg.nDevices+1){Bool(false)})
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val enables = Reg(Vec(cfg.nHarts, UInt(width = cfg.nDevices+1)))
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val threshold = Reg(Vec(cfg.nHarts, UInt(width = log2Up(cfg.nPriorities+1))))
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for ((p, g) <- pending.tail zip io.devices) {
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g.ready := !p
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g.complete := false
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when (g.valid) { p := true }
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}
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def findMax(x: Seq[UInt]): (UInt, UInt) = {
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if (x.length > 1) {
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val half = 1 << (log2Ceil(x.length) - 1)
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val lMax = findMax(x take half)
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val rMax = findMax(x drop half)
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val useLeft = lMax._1 >= rMax._1
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) + rMax._2))
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} else (x.head, UInt(0))
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}
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val maxDevs = Wire(Vec(cfg.nHarts, UInt(width = log2Up(pending.size))))
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for (hart <- 0 until cfg.nHarts) {
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val effectivePriority =
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2016-05-10 23:15:47 +02:00
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for (((p, en), pri) <- (pending zip enables(hart).toBools zip priority).tail)
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2016-05-10 09:25:13 +02:00
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yield Cat(p && en, pri)
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2016-05-10 23:15:47 +02:00
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val (_, maxDev) = findMax(Cat(UInt(1), threshold(hart)) +: effectivePriority)
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2016-05-10 09:25:13 +02:00
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2016-05-10 23:15:47 +02:00
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maxDevs(hart) := Reg(next = maxDev)
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io.harts(hart) := maxDevs(hart) =/= 0
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2016-05-10 09:25:13 +02:00
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}
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val acq = Queue(io.tl.acquire, 1)
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2016-06-02 22:47:59 +02:00
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val read = acq.fire() && acq.bits.isBuiltInType(Acquire.getType)
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val write = acq.fire() && acq.bits.isBuiltInType(Acquire.putType)
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assert(!acq.fire() || read || write, "unsupported PLIC operation")
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2016-05-10 09:25:13 +02:00
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val addr = acq.bits.full_addr()(log2Up(cfg.size)-1,0)
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val claimant =
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if (cfg.nHarts == 1) UInt(0)
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else (addr - cfg.hartBase)(log2Up(cfg.hartOffset(cfg.nHarts))-1,log2Up(cfg.hartOffset(1)))
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val hart = Wire(init = claimant)
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val myMaxDev = maxDevs(claimant) + UInt(0) // XXX FIRRTL bug w/o the + UInt(0)
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val myEnables = enables(hart) >> 1 << 1
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2016-05-10 23:15:47 +02:00
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val rdata = Wire(init = Cat(myMaxDev, UInt(0, 16-threshold(0).getWidth), threshold(claimant)))
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val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
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2016-05-10 09:25:13 +02:00
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when (addr >= cfg.hartBase) {
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when (read && addr(log2Ceil(cfg.claimOffset))) {
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pending(myMaxDev) := false
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}.elsewhen (write && acq.bits.wmask()(cfg.claimOffset)) {
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val dev = (acq.bits.data >> (8 * cfg.claimOffset))(log2Up(pending.size)-1,0)
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2016-06-02 22:47:59 +02:00
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when (myEnables(dev)) { io.devices(dev-1).complete := true }
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2016-05-10 09:25:13 +02:00
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}.elsewhen (write) {
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val thresh = acq.bits.data(log2Up(pending.size)-1,0)
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2016-06-02 22:47:59 +02:00
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threshold(claimant) := thresh
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2016-05-10 09:25:13 +02:00
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}
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}.elsewhen (addr >= cfg.enableBase) {
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2016-05-10 23:15:47 +02:00
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rdata := myEnables
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2016-05-10 09:25:13 +02:00
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if (cfg.nHarts > 1)
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hart := (addr - cfg.enableBase)(log2Up(cfg.enableOffset(cfg.nHarts))-1,log2Up(cfg.enableOffset(1)))
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require(enables.size <= tlDataBits) // TODO this can be relaxed
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when (write) { enables(hart) := masked_wdata >> 1 << 1 }
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}.elsewhen (addr >= cfg.pendingBase) {
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for (i <- 0 until pending.size by tlDataBytes) {
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val cond =
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if (tlDataBytes >= pending.size) Bool(true)
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else addr(log2Up(pending.size)-1,log2Up(tlDataBytes)) === i/tlDataBytes
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when (cond) {
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2016-05-10 23:15:47 +02:00
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rdata := Cat(pending.slice(i, i + tlDataBytes).map(p => Cat(UInt(0, 7), p)).reverse)
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2016-05-10 09:25:13 +02:00
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for (j <- 0 until (tlDataBytes min (pending.size - i))) {
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when (write) { pending(i+j) := masked_wdata(j * 8) }
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}
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}
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}
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}.otherwise {
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val regAddrBits = log2Up(log2Up(cfg.maxDevices+1)) - 3
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val regsPerBeat = tlDataBytes >> regAddrBits
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for (i <- 0 until priority.size by regsPerBeat) {
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val cond =
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if (regsPerBeat >= priority.size) Bool(true)
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else addr(log2Up(priority.size)+regAddrBits-1,log2Up(tlDataBytes)) === i/regsPerBeat
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when (cond) {
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2016-05-10 23:15:47 +02:00
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rdata := Cat(priority.slice(i, i + regsPerBeat).map(p => Cat(UInt(0, 16-p.getWidth), p)).reverse)
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2016-05-10 09:25:13 +02:00
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for (j <- 0 until (regsPerBeat min (priority.size - i))) {
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2016-06-02 22:48:29 +02:00
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if (cfg.nPriorities > 0) when (write) { priority(i+j) := masked_wdata >> (j * (8 << regAddrBits)) }
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2016-05-10 09:25:13 +02:00
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}
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}
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}
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}
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priority(0) := 0
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pending(0) := false
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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}
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