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rocket-chip/rocket/src/main/scala/rocc.scala

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Scala
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package rocket
import Chisel._
import Node._
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import uncore._
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class RoCCInstruction extends Bundle
{
val funct = Bits(width = 7)
val rs2 = Bits(width = 5)
val rs1 = Bits(width = 5)
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val xd = Bool()
val xs1 = Bool()
val xs2 = Bool()
val rd = Bits(width = 5)
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val opcode = Bits(width = 7)
}
class RoCCCommand(implicit conf: RocketConfiguration) extends Bundle
{
val inst = new RoCCInstruction
val rs1 = Bits(width = conf.xprlen)
val rs2 = Bits(width = conf.xprlen)
override def clone = new RoCCCommand().asInstanceOf[this.type]
}
class RoCCResponse(implicit conf: RocketConfiguration) extends Bundle
{
val rd = Bits(width = 5)
val data = Bits(width = conf.xprlen)
override def clone = new RoCCResponse().asInstanceOf[this.type]
}
class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
{
val cmd = Decoupled(new RoCCCommand).flip
val resp = Decoupled(new RoCCResponse)
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val mem = new HellaCacheIO()(conf.dcache)
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val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT)
override def clone = new RoCCInterface().asInstanceOf[this.type]
}
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abstract class RoCC(conf: RocketConfiguration) extends Module
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{
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val io = new RoCCInterface()(conf)
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}
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class AccumulatorExample(conf: RocketConfiguration) extends RoCC(conf)
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{
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val n = 4
val regfile = Mem(UInt(width = conf.xprlen), n)
val busy = Vec.fill(n){Reg(init=Bool(false))}
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val cmd = Queue(io.cmd)
val funct = cmd.bits.inst.funct
val addr = cmd.bits.inst.rs2(log2Up(n)-1,0)
val doWrite = funct === UInt(0)
val doRead = funct === UInt(1)
val doLoad = funct === UInt(2)
val doAccum = funct === UInt(3)
val memRespTag = io.mem.resp.bits.tag(log2Up(n)-1,0)
// datapath
val addend = cmd.bits.rs1
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val accum = regfile(addr)
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val wdata = Mux(doWrite, addend, accum + addend)
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when (cmd.fire() && (doWrite || doAccum)) {
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regfile(addr) := wdata
}
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when (io.mem.resp.valid) {
regfile(memRespTag) := io.mem.resp.bits.data
}
// control
when (io.mem.req.fire()) {
busy(addr) := Bool(true)
}
when (io.mem.resp.valid) {
busy(memRespTag) := Bool(false)
}
val doResp = cmd.bits.inst.xd
val stallReg = busy(addr)
val stallLoad = doLoad && !io.mem.req.ready
val stallResp = doResp && !io.resp.ready
cmd.ready := !stallReg && !stallLoad && !stallResp
// command resolved if no stalls AND not issuing a load that will need a request
// note, loadSent = true will occur when the load response comes back
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
// valid response if valid command, need a response, and no stalls
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io.resp.bits.rd := cmd.bits.inst.rd
io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value
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io.busy := Bool(false)
io.interrupt := Bool(false)
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io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
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io.mem.req.bits.addr := addend
io.mem.req.bits.tag := addr
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io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores...
io.mem.req.bits.phys := Bool(true) // don't perform address translation
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}