2016-09-08 11:08:57 +02:00
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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2016-11-18 23:05:14 +01:00
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import config._
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2016-09-08 11:08:57 +02:00
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import junctions._
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2016-09-13 19:47:36 +02:00
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import junctions.NastiConstants._
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2016-10-04 00:17:36 +02:00
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import diplomacy._
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2016-09-08 11:08:57 +02:00
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import uncore.tilelink._
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2016-09-15 03:09:27 +02:00
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import uncore.tilelink2._
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2016-10-26 01:27:42 +02:00
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import uncore.axi4._
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2016-09-08 11:08:57 +02:00
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import uncore.converters._
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import uncore.devices._
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2016-09-24 00:25:58 +02:00
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import uncore.agents._
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2016-09-08 11:08:57 +02:00
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import uncore.util._
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2016-09-28 06:27:07 +02:00
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import util._
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2016-09-16 07:06:39 +02:00
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import rocket.XLen
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import scala.math.max
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2016-09-08 11:08:57 +02:00
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import coreplex._
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/** Specifies the size of external memory */
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2016-11-24 00:37:08 +01:00
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case class MasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
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case object ExtMem extends Field[MasterConfig]
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case object ExtBus extends Field[MasterConfig]
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case class SlaveConfig(beatBytes: Int, idBits: Int, sourceBits: Int)
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case object ExtIn extends Field[SlaveConfig]
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2016-09-11 08:39:29 +02:00
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/** Specifies the number of external interrupts */
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2016-09-08 11:08:57 +02:00
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case object NExtTopInterrupts extends Field[Int]
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/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
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case object RTCPeriod extends Field[Int]
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2016-09-24 00:25:58 +02:00
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/* Specifies the periphery bus configuration */
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2016-11-17 23:07:53 +01:00
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case object PeripheryBusConfig extends Field[TLBusConfig]
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case object PeripheryBusArithmetic extends Field[Boolean]
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2016-10-25 08:56:09 +02:00
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/* Specifies the SOC-bus configuration */
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2016-11-17 23:07:53 +01:00
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case object SOCBusConfig extends Field[TLBusConfig]
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/** Utility trait for quick access to some relevant parameters */
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trait HasPeripheryParameters {
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implicit val p: Parameters
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2016-11-17 23:07:53 +01:00
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lazy val peripheryBusConfig = p(PeripheryBusConfig)
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lazy val socBusConfig = p(SOCBusConfig)
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2016-09-24 00:25:58 +02:00
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lazy val cacheBlockBytes = p(CacheBlockBytes)
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2016-11-17 23:07:53 +01:00
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lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
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2016-09-08 11:08:57 +02:00
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}
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/////
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2016-10-29 07:30:13 +02:00
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trait PeripheryExtInterrupts {
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this: TopNetwork =>
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2016-09-11 08:39:29 +02:00
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2016-10-29 06:20:49 +02:00
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val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
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val extInterruptXing = LazyModule(new IntXing)
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intBus.intnode := extInterruptXing.intnode
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extInterruptXing.intnode := extInterrupts
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2016-09-08 11:08:57 +02:00
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}
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2016-09-11 08:39:29 +02:00
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trait PeripheryExtInterruptsBundle {
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this: TopNetworkBundle {
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val outer: PeripheryExtInterrupts
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} =>
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val interrupts = outer.extInterrupts.bundleIn
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2016-09-08 11:08:57 +02:00
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}
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2016-09-11 08:39:29 +02:00
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trait PeripheryExtInterruptsModule {
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2016-10-29 07:30:13 +02:00
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this: TopNetworkModule {
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val outer: PeripheryExtInterrupts
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val io: PeripheryExtInterruptsBundle
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} =>
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2016-09-08 11:08:57 +02:00
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}
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/////
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2016-11-04 05:31:26 +01:00
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trait PeripheryMasterAXI4Mem {
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2016-11-23 00:01:45 +01:00
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this: TopNetwork =>
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val module: PeripheryMasterAXI4MemModule
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2016-11-04 05:31:26 +01:00
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2016-11-18 00:38:11 +01:00
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private val config = p(ExtMem)
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2016-11-23 00:01:45 +01:00
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private val channels = p(BankedL2Config).nMemoryChannels
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2016-11-04 05:31:26 +01:00
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2016-11-23 00:01:45 +01:00
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val mem_axi4 = Seq.tabulate(channels) { i =>
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2016-11-18 00:38:11 +01:00
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val c_size = config.size/channels
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val c_base = config.base + c_size*i
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2016-11-04 05:31:26 +01:00
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2016-11-23 00:01:45 +01:00
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AXI4BlindOutputNode(AXI4SlavePortParameters(
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2016-11-04 05:31:26 +01:00
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(c_base, c_size-1)),
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2016-11-15 00:19:39 +01:00
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regionType = RegionType.UNCACHED, // cacheable
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executable = true,
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supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
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supportsRead = TransferSizes(1, 256),
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interleavedId = Some(0))), // slave does not interleave read responses
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2016-11-18 00:38:11 +01:00
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beatBytes = config.beatBytes))
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2016-11-23 00:01:45 +01:00
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}
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2016-11-04 05:31:26 +01:00
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2016-11-23 00:01:45 +01:00
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val mem = mem_axi4.map { node =>
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val foo = LazyModule(new TLToAXI4(config.idBits))
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node := foo.node
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foo.node
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2016-11-04 05:31:26 +01:00
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}
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2016-09-08 11:08:57 +02:00
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}
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2016-11-04 05:31:26 +01:00
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trait PeripheryMasterAXI4MemBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterAXI4Mem
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2016-10-29 07:30:13 +02:00
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} =>
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val mem_axi4 = outer.mem_axi4.map(_.bundleOut).toList.headOption // !!! remove headOption when Seq supported
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2016-09-08 11:08:57 +02:00
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}
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2016-11-04 05:31:26 +01:00
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trait PeripheryMasterAXI4MemModule {
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this: TopNetworkModule {
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2016-11-04 05:31:26 +01:00
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val outer: PeripheryMasterAXI4Mem
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val io: PeripheryMasterAXI4MemBundle
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2016-10-29 07:30:13 +02:00
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} =>
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2016-09-08 11:08:57 +02:00
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}
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/////
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2016-10-26 01:27:42 +02:00
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// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
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2016-10-29 07:30:13 +02:00
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trait PeripheryMasterAXI4MMIO {
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this: TopNetwork =>
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2016-10-26 01:27:42 +02:00
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2016-11-18 00:38:11 +01:00
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private val config = p(ExtBus)
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2016-10-26 01:27:42 +02:00
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val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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2016-11-18 00:38:11 +01:00
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address = List(AddressSet(BigInt(config.base), config.size-1)),
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2016-10-26 01:27:42 +02:00
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executable = true, // Can we run programs on this memory?
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supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
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supportsRead = TransferSizes(1, 256),
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interleavedId = Some(0))), // slave does not interleave read responses
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2016-11-18 00:38:11 +01:00
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beatBytes = config.beatBytes))
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2016-10-26 01:27:42 +02:00
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mmio_axi4 :=
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// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
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TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
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2016-10-26 01:27:42 +02:00
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TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus
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socBus.node))
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2016-09-08 11:08:57 +02:00
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}
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2016-10-29 07:30:13 +02:00
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trait PeripheryMasterAXI4MMIOBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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2016-11-23 01:58:24 +01:00
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val mmio_axi4 = outer.mmio_axi4.bundleOut
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2016-09-08 11:08:57 +02:00
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}
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2016-10-29 07:30:13 +02:00
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trait PeripheryMasterAXI4MMIOModule {
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this: TopNetworkModule {
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val outer: PeripheryMasterAXI4MMIO
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val io: PeripheryMasterAXI4MMIOBundle
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} =>
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2016-10-26 01:27:42 +02:00
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// nothing to do
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2016-09-08 11:08:57 +02:00
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}
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/////
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2016-11-23 01:58:24 +01:00
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// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
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trait PeripherySlaveAXI4 extends L2Crossbar {
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2016-11-24 00:37:08 +01:00
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private val config = p(ExtIn)
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2016-11-23 01:58:24 +01:00
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val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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2016-11-24 00:37:08 +01:00
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id = IdRange(0, 1 << config.idBits)))))
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l2.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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l2_axi4))))
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2016-11-23 01:58:24 +01:00
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}
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trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
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val outer: PeripherySlaveAXI4
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val l2_axi4 = outer.l2_axi4.bundleIn
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}
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trait PeripherySlaveAXI4Module extends L2CrossbarModule {
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val outer: PeripherySlaveAXI4
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val io: PeripherySlaveAXI4Bundle
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// nothing to do
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}
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/////
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2016-11-24 00:37:08 +01:00
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// Add an external TL-UL slave
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trait PeripheryMasterTLMMIO {
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this: TopNetwork =>
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private val config = p(ExtBus)
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val mmio_tl = TLBlindOutputNode(TLManagerPortParameters(
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managers = Seq(TLManagerParameters(
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address = List(AddressSet(BigInt(config.base), config.size-1)),
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executable = true,
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supportsGet = TransferSizes(1, cacheBlockBytes),
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supportsPutFull = TransferSizes(1, cacheBlockBytes),
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supportsPutPartial = TransferSizes(1, cacheBlockBytes))),
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beatBytes = config.beatBytes))
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mmio_tl :=
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TLSourceShrinker(config.idBits)(
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TLWidthWidget(socBusConfig.beatBytes)(
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socBus.node))
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}
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trait PeripheryMasterTLMMIOBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterTLMMIO
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} =>
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val mmio_tl = outer.mmio_tl.bundleOut
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}
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trait PeripheryMasterTLMMIOModule {
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this: TopNetworkModule {
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val outer: PeripheryMasterTLMMIO
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val io: PeripheryMasterTLMMIOBundle
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} =>
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// nothing to do
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}
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/////
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// NOTE: this port is NOT allowed to issue Acquires
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trait PeripherySlaveTL extends L2Crossbar {
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private val config = p(ExtIn)
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val l2_tl = TLBlindInputNode(TLClientPortParameters(
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clients = Seq(TLClientParameters(
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sourceId = IdRange(0, 1 << config.idBits)))))
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l2.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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l2_tl))
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}
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trait PeripherySlaveTLBundle extends L2CrossbarBundle {
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val outer: PeripherySlaveTL
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val l2_tl = outer.l2_tl.bundleIn
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}
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trait PeripherySlaveTLModule extends L2CrossbarModule {
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val outer: PeripherySlaveTL
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val io: PeripherySlaveTLBundle
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// nothing to do
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}
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/////
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2016-10-29 07:30:13 +02:00
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trait PeripheryBootROM {
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this: TopNetwork =>
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2016-11-22 01:11:16 +01:00
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val coreplex: CoreplexRISCVPlatform
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2016-09-15 03:09:27 +02:00
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2016-11-22 01:11:16 +01:00
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private val bootrom_address = 0x1000
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private val bootrom_size = 0x1000
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private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
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val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
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2016-10-15 00:11:13 +02:00
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bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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2016-09-15 01:09:59 +02:00
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}
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trait PeripheryBootROMBundle {
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2016-10-29 07:30:13 +02:00
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this: TopNetworkBundle {
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val outer: PeripheryBootROM
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} =>
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2016-09-15 01:09:59 +02:00
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}
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2016-10-29 07:30:13 +02:00
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trait PeripheryBootROMModule {
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this: TopNetworkModule {
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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} =>
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2016-09-15 01:09:59 +02:00
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}
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/////
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2016-10-29 07:30:13 +02:00
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trait PeripheryTestRAM {
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this: TopNetwork =>
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2016-09-15 03:09:27 +02:00
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2016-10-29 07:30:13 +02:00
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
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testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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2016-09-11 08:39:29 +02:00
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}
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trait PeripheryTestRAMBundle {
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2016-10-29 07:30:13 +02:00
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this: TopNetworkBundle {
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val outer: PeripheryTestRAM
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} =>
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2016-09-11 08:39:29 +02:00
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}
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2016-10-29 07:30:13 +02:00
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trait PeripheryTestRAMModule {
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this: TopNetworkModule {
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val outer: PeripheryTestRAM
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val io: PeripheryTestRAMBundle
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} =>
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2016-09-11 08:39:29 +02:00
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}
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/////
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2016-10-29 07:30:13 +02:00
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trait PeripheryTestBusMaster {
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this: TopNetwork =>
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2016-09-15 03:09:27 +02:00
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val fuzzer = LazyModule(new TLFuzzer(5000))
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peripheryBus.node := fuzzer.node
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2016-09-11 08:39:29 +02:00
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}
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trait PeripheryTestBusMasterBundle {
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2016-10-29 07:30:13 +02:00
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this: TopNetworkBundle {
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val outer: PeripheryTestBusMaster
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} =>
|
2016-09-11 08:39:29 +02:00
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}
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|
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trait PeripheryTestBusMasterModule {
|
2016-10-29 07:30:13 +02:00
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this: TopNetworkModule {
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val outer: PeripheryTestBusMaster
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val io: PeripheryTestBusMasterBundle
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} =>
|
2016-09-08 11:08:57 +02:00
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}
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