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rocket-chip/vsim/Makefrag

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#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
# Verilog sources
bb_vsrcs = \
$(base_dir)/vsrc/plusarg_reader.v \
$(base_dir)/vsrc/ClockDivider2.v \
$(base_dir)/vsrc/ClockDivider3.v \
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$(base_dir)/vsrc/AsyncResetReg.v \
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sim_vsrcs = \
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$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
$(base_dir)/vsrc/SimJTAG.v \
$(bb_vsrcs)
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# C sources
sim_csrcs = \
$(base_dir)/csrc/SimDTM.cc \
$(base_dir)/csrc/SimJTAG.cc \
$(base_dir)/csrc/remote_bitbang.cc
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#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
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#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
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+libext+.v \
#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------
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simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
-debug_pp \
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simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
+define+DEBUG -debug_pp \
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
seed = $(shell date +%s)
exec_simv = $(simv) +permissive -q +ntb_random_seed_automatic +permissive-off
exec_simv_debug = $(simv_debug) +permissive -q +ntb_random_seed_automatic +permissive-off