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rocket-chip/vsim/Makefrag

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update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
# Verilog sources
sim_vsrcs = \
add CONFIG to the name of simulator executable
2014-09-12 07:11:58 +02:00
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/consts.$(CONFIG).vh \
add Zscale testing
2015-07-17 21:02:02 +02:00
$(base_dir)/vsrc/$(TB).v \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(base_dir)/vsrc/SimDTM.v \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
# C sources
sim_csrcs = \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(base_dir)/csrc/SimDTM.cc \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
fix problem introduced with verilog generation in vsim/fsim
2014-09-04 18:49:57 +02:00
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
VCS = vcs -full64
error out for PCWM-L, port width mismatch
2014-09-25 15:43:03 +02:00
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
no spaces in Makefrag
2015-11-06 01:42:05 +01:00
-CC "-include $(consts_header)" \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(RISCV)/lib/libfesvr.so \
Exit from testbench, not C code Otherwise, we don't get coverage data from the simulator.
2016-06-24 05:54:07 +02:00
-sverilog \
add multichannel NASTI support in Verilog testbench
2015-10-31 05:14:33 +01:00
+incdir+$(generated_dir) \
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 23:44:48 +02:00
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
Disable printf/assert during reset
2016-04-02 01:40:13 +02:00
+define+PRINTF_COND=$(TB).printf_cond \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
+define+STOP_COND=!$(TB).reset \
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-08 04:34:03 +02:00
+define+RANDOMIZE \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
+libext+.v \
#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 09:23:31 +02:00
simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
cd $(sim_dir) && \
no spaces in Makefrag
2015-11-06 01:42:05 +01:00
rm -rf csrc && \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(VCS) $(VCS_OPTS) -o $(simv) \
Massive update containing several months of changes from the now-defunct private chip repo. * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
2015-06-26 08:17:35 +02:00
-debug_pp \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 09:23:31 +02:00
simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
cd $(sim_dir) && \
no spaces in Makefrag
2015-11-06 01:42:05 +01:00
rm -rf csrc && \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(VCS) $(VCS_OPTS) -o $(simv_debug) \
+define+DEBUG -debug_pp \
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
seed = $(shell date +%s)
exec_simv = $(simv) -q +ntb_random_seed_automatic
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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