2017-07-23 17:31:04 +02:00
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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2017-10-20 04:48:20 +02:00
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import chisel3.internal.sourceinfo.SourceInfo
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2017-07-23 17:31:04 +02:00
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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2017-10-20 05:44:54 +02:00
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import freechips.rocketchip.interrupts._
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2017-07-23 17:31:04 +02:00
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import freechips.rocketchip.util._
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2017-10-10 08:43:18 +02:00
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// TODO: how specific are these to RocketTiles?
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2017-10-11 00:02:50 +02:00
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case class TileMasterPortParams(
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addBuffers: Int = 0,
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2017-10-11 01:24:32 +02:00
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cork: Option[Boolean] = None) {
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2017-10-23 18:39:01 +02:00
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2017-10-20 04:48:20 +02:00
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def adapt(coreplex: HasPeripheryBus)
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(masterNode: TLOutwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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2017-10-11 01:24:32 +02:00
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val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u))))
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2017-10-11 00:02:50 +02:00
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val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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2017-10-11 09:29:11 +02:00
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2017-11-18 02:26:48 +01:00
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(Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers) ++ tile_master_cork.map(_.node))
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.foldRight(masterNode)(_ :=* _)
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2017-10-11 00:02:50 +02:00
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}
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}
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case class TileSlavePortParams(
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addBuffers: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None) {
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2017-10-23 18:39:01 +02:00
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2017-10-20 04:48:20 +02:00
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def adapt(coreplex: HasPeripheryBus)
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2017-10-25 11:27:01 +02:00
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(slaveNode: TLInwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
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2017-10-20 04:48:20 +02:00
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val tile_slave_blocker =
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blockerCtrlAddr
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2017-11-18 23:32:37 +01:00
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.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
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2017-10-20 04:48:20 +02:00
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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2017-10-11 09:29:11 +02:00
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2017-10-23 18:39:01 +02:00
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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2017-10-25 23:45:44 +02:00
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(Seq() ++ tile_slave_blocker.map(_.node) ++ TLBuffer.chain(addBuffers))
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2017-10-25 11:27:01 +02:00
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.foldLeft(slaveNode)(_ :*= _)
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2017-10-11 00:02:50 +02:00
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}
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}
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2017-10-10 08:43:18 +02:00
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case class RocketCrossingParams(
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crossingType: CoreplexClockCrossing = SynchronousCrossing(),
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master: TileMasterPortParams = TileMasterPortParams(),
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2017-10-26 22:52:34 +02:00
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slave: TileSlavePortParams = TileSlavePortParams()) {
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2017-10-10 08:43:18 +02:00
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def knownRatio: Option[Int] = crossingType match {
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case RationalCrossing(_) => Some(2)
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case _ => None
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}
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}
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2017-09-09 03:33:44 +02:00
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case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
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2017-10-10 08:43:18 +02:00
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case object RocketCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams()))
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2017-07-23 17:31:04 +02:00
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2017-10-06 09:56:23 +02:00
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trait HasRocketTiles extends HasTiles
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2017-07-23 17:31:04 +02:00
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with HasPeripheryBus
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with HasPeripheryPLIC
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with HasPeripheryClint
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with HasPeripheryDebug {
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val module: HasRocketTilesModuleImp
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2017-12-14 04:00:29 +01:00
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protected val rocketTileParams = p(RocketTilesKey)
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private val NumRocketTiles = rocketTileParams.size
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2017-10-10 08:43:18 +02:00
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private val crossingParams = p(RocketCrossingKey)
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private val crossings = crossingParams.size match {
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case 1 => List.fill(NumRocketTiles) { crossingParams.head }
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case NumRocketTiles => crossingParams
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case _ => throw new Exception("RocketCrossingKey.size must == 1 or == RocketTilesKey.size")
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}
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private val crossingTuples = rocketTileParams.zip(crossings)
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2017-07-23 17:31:04 +02:00
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// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
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// according to the specified type of clock crossing.
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2017-12-14 04:00:29 +01:00
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val rocketTiles = crossingTuples.map { case (tp, crossing) =>
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2017-10-23 18:39:01 +02:00
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// For legacy reasons, it is convenient to store some state
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// in the global Parameters about the specific tile being built now
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val wrapper = LazyModule(new RocketTileWrapper(
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params = tp,
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2017-10-26 22:52:34 +02:00
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crossing = crossing.crossingType
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2017-10-23 18:39:01 +02:00
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)(p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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case SharedMemoryTLEdge => sharedMemoryTLEdge
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case RocketCrossingKey => List(crossing)
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})
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).suggestName(tp.name)
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// Connect the master ports of the tile to the system bus
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2017-10-25 23:45:44 +02:00
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sbus.fromTile(tp.name) { implicit p => crossing.master.adapt(this)(wrapper.crossTLOut :=* wrapper.masterNode) }
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2017-10-23 18:39:01 +02:00
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// Connect the slave ports of the tile to the periphery bus
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2017-10-25 23:45:44 +02:00
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pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(wrapper.slaveNode :*= wrapper.crossTLIn) }
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2017-10-23 18:39:01 +02:00
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// Handle all the different types of interrupts crossing to or from the tile:
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// 1. Debug interrupt is definitely asynchronous in all cases.
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// 2. The CLINT and PLIC output interrupts are synchronous to the periphery clock,
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// so might need to be synchronized depending on the Tile's crossing type.
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// 3. Local Interrupts are required to already be synchronous to the tile clock.
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// 4. Interrupts coming out of the tile are sent to the PLIC,
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// so might need to be synchronized depending on the Tile's crossing type.
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// NOTE: The order of calls to := matters! They must match how interrupts
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// are decoded from rocket.intNode inside the tile.
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2017-12-14 04:00:29 +01:00
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// 1. always async crossing for debug
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2017-12-21 02:18:38 +01:00
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wrapper.intInwardNode := wrapper { IntSyncCrossingSink(3) } := debug.intnode
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2017-10-26 01:13:55 +02:00
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2017-12-14 04:00:29 +01:00
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// 2. clint+plic conditionally crossing
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2017-12-21 02:18:38 +01:00
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val periphIntNode = wrapper.intInwardNode :=* wrapper.crossIntIn
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2017-10-26 01:13:55 +02:00
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periphIntNode := clint.intnode // msip+mtip
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periphIntNode := plic.intnode // meip
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if (tp.core.useVM) periphIntNode := plic.intnode // seip
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2017-12-14 04:00:29 +01:00
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// 3. local interrupts never cross
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2017-12-21 02:18:38 +01:00
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// this.intInwardNode is wired up externally // lip
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2017-10-26 01:13:55 +02:00
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2017-12-14 04:00:29 +01:00
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// 4. conditional crossing from core to PLIC
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2017-12-21 02:18:38 +01:00
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FlipRendering { implicit p =>
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plic.intnode :=* wrapper.crossIntOut :=* wrapper.intOutwardNode
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2017-09-27 21:02:04 +02:00
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}
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2017-09-16 03:49:40 +02:00
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2017-07-23 17:31:04 +02:00
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wrapper
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}
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}
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2017-10-08 02:29:50 +02:00
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trait HasRocketTilesModuleImp extends HasTilesModuleImp
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2017-07-23 17:31:04 +02:00
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with HasPeripheryDebugModuleImp {
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2017-10-08 02:29:50 +02:00
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val outer: HasRocketTiles
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2017-07-23 17:31:04 +02:00
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}
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class RocketCoreplex(implicit p: Parameters) extends BaseCoreplex
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with HasRocketTiles {
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2017-12-14 04:00:29 +01:00
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val tiles = rocketTiles
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2017-07-23 17:31:04 +02:00
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override lazy val module = new RocketCoreplexModule(this)
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}
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class RocketCoreplexModule[+L <: RocketCoreplex](_outer: L) extends BaseCoreplexModule(_outer)
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2017-12-14 04:00:29 +01:00
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with HasRocketTilesModuleImp {
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tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
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wire.clock := clock
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wire.reset := reset
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wire.hartid := UInt(i)
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wire.reset_vector := global_reset_vector
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}
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}
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