6 Commits

6 changed files with 21 additions and 70 deletions

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@ -8,7 +8,7 @@
.globl _prog_start
_prog_start:
smp_pause(s1, s2)
li sp, (PAYLOAD_DEST + 0xffff000)
li sp, (PAYLOAD_DEST + 0x7fff000)
call main
smp_resume(s1, s2)
csrr a0, mhartid

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@ -20,8 +20,7 @@ static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR);
static inline void kputc(char c)
{
//volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
volatile uint32_t *tx = (void *) 0x64003000; // Terminal (32 bit)
volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
#ifdef __riscv_atomic
int32_t r;
do {
@ -34,6 +33,9 @@ static inline void kputc(char c)
while ((int32_t)(*tx) < 0);
*tx = c;
#endif
volatile uint32_t *term = (void *) 0x64003000; // Terminal (32 bit)
while ((int32_t)(*term) < 0);
*term = c;
}
extern void kputs(const char *);

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@ -10,7 +10,11 @@
#define MAX_CORES 8
#define PAYLOAD_SIZE (16 << 11)
//#define PAYLOAD_START 0
//#define PAYLOAD_CRC7 0xE1
#define PAYLOAD_START 2048
#define PAYLOAD_CRC7 0x51
#define PAYLOAD_SIZE (16 << 12)
#define F_CLK 60000000UL
@ -160,11 +164,10 @@ static int copy(void)
int rc = 0;
dputs("CMD18");
//~ kprintf("LOADING ");
kprintf("READ: ");
kprintf("LOADING ");
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
if (sd_cmd(0x52, PAYLOAD_START, PAYLOAD_CRC7) != 0x00) {
sd_cmd_end();
return 1;
}
@ -173,18 +176,14 @@ static int copy(void)
long n;
crc = 0;
//~ n = 512;
n = 50;
n = 512;
while (sd_dummy() != 0xFE);
do {
uint8_t x = sd_dummy();
kputc(x);
//~ *p++ = x;
//~ crc = crc16_round(crc, x);
*p++ = x;
crc = crc16_round(crc, x);
} while (--n > 0);
return 0;
crc_exp = ((uint16_t)sd_dummy() << 8);
crc_exp |= sd_dummy();
@ -207,60 +206,10 @@ static int copy(void)
return rc;
}
// leave room for 2 MiB stack (SP = 8FFFF000)
#define RAMTEST_START (uint32_t*)(0x80000000)
#define RAMTEST_END (uint32_t*)(0x8FDFF000)
int main(void)
{
//REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
//GPIO_REG(GPIO_INPUT_EN) = 0xFF;
GPIO_REG(GPIO_OUTPUT_EN) = 0xFF;
GPIO_REG(GPIO_OUTPUT_VAL) = 0xFF;
kprintf("\nFilling RAM from %lx to %lx...\n", RAMTEST_START, RAMTEST_END);
uint32_t counter = 0;
for(uint32_t* ram = RAMTEST_START; ram < RAMTEST_END; ++ram) {
*ram = counter++;
}
kprintf("\rChecking RAM...\n");
counter = 0;
uint32_t correct = 0;
uint32_t wrong = 0;
for(uint32_t* ram = RAMTEST_START; ram < RAMTEST_END; ++ram) {
if(*ram != counter) {
kprintf("\rMismatch at %lx: read %x, expected %x\n", ram, *ram, counter);
++wrong;
} else {
++correct;
}
++counter;
}
kprintf("\rSummary: %x matches, %x mismatches.\n", correct, wrong);
kprintf("\nTrying to read from SD card...\n");
kputs("POWERON");
sd_poweron();
kprintf("sd_cmd0: %hx\n", sd_cmd0());
kprintf("sd_cmd8: %hx\n", sd_cmd8());
kprintf("sd_acmd41: %hx\n", sd_acmd41());
kprintf("sd_cmd58: %hx\n", sd_cmd58());
kprintf("sd_cmd16: %hx\n", sd_cmd16());
kprintf("\ncopy: %hx\n", copy());
while(1) {
//uint8_t dip_value = GPIO_REG(GPIO_INPUT_VAL) & 0b01111111;
//kprintf("dip value: %hx, ram value: %c\n", dip_value, ram[dip_value]);
GPIO_REG(GPIO_OUTPUT_VAL) ^= 0xFF;
}
return 0;
/*
kputs("INIT");
sd_poweron();
if (sd_cmd0() ||
@ -276,5 +225,5 @@ int main(void)
kputs("BOOT");
__asm__ __volatile__ ("fence.i" : : : "memory");
return 0;*/
return 0;
}

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@ -63,7 +63,7 @@ endif
verilog: $(verilog)
romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
$(romgen): $(verilog)
$(romgen): $(verilog) $(BOOTROM_DIR)
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) romgen
mv $(BUILD_DIR)/rom.v $@

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@ -20,8 +20,9 @@ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
class FreedomUML507Config extends Config(
new WithoutTLMonitors ++
new WithJtagDTM ++
new WithClockFrequency(60000000) ++ // 60 MHz
new WithNMemoryChannels(1) ++
new WithNBigCores(1) ++
new WithNSmallLinuxCores(1) ++
new BaseConfig
)
@ -45,7 +46,6 @@ class U500ML507DevKitConfig extends Config(
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x10000000L)