3 Commits

Author	SHA1	Message	Date
Richard Xia	f4375c2266	Add variable to control what program gets flashed to FPGA.	2016-12-08 12:14:17 -08:00
Richard Xia	c14985f3a7	Remove verilog header files built from Chisel .prm file.	2016-11-30 14:30:05 -08:00
SiFive	3cf8128a30	Initial commit.	2016-11-29 05:23:11 -08:00