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ml507: Remove redundant clock definition

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This commit is contained in:
Klemens Schölhorn 2018-04-24 00:49:39 +02:00
parent c10d2378e7
commit d749f87696
1 changed files with 0 additions and 2 deletions
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src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
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@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
// DUT // DUT
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
// Connect the clock to the 50 Mhz output from the PLL
dut_clock := clk50
withClockAndReset(dut_clock, dut_reset) { withClockAndReset(dut_clock, dut_reset) {
val dut = Module(LazyModule(new U500ML507DevKitSystem).module) val dut = Module(LazyModule(new U500ML507DevKitSystem).module)