diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
index c10df12..178e087 100644
--- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
@@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
   // DUT
   //-----------------------------------------------------------------------
 
-  // Connect the clock to the 50 Mhz output from the PLL
-  dut_clock := clk50
   withClockAndReset(dut_clock, dut_reset) {
     val dut = Module(LazyModule(new U500ML507DevKitSystem).module)