From d749f87696bc85874b25ca8f50cd60130d3b6463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Tue, 24 Apr 2018 00:49:39 +0200 Subject: [PATCH] ml507: Remove redundant clock definition --- src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala index c10df12..178e087 100644 --- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala +++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala @@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters) // DUT //----------------------------------------------------------------------- - // Connect the clock to the 50 Mhz output from the PLL - dut_clock := clk50 withClockAndReset(dut_clock, dut_reset) { val dut = Module(LazyModule(new U500ML507DevKitSystem).module)