ml507: Remove redundant clock definition

2018-04-24 00:49:39 +02:00
parent c10d2378e7
commit d749f87696
1 changed files with 0 additions and 2 deletions
--- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
@@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
  // DUT
  //-----------------------------------------------------------------------

-  // Connect the clock to the 50 Mhz output from the PLL
-  dut_clock := clk50
  withClockAndReset(dut_clock, dut_reset) {
    val dut = Module(LazyModule(new U500ML507DevKitSystem).module)