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Switch to new XilinxML507MIG and connect top level signals

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This commit is contained in:
Klemens Schölhorn 2018-05-10 00:37:00 +02:00
parent 7b46ed6b7c
commit 291a765b8d
4 changed files with 7 additions and 5 deletions
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2
fpga-shells

@ -1 +1 @@
Subproject commit 79b53cf2ae2478f20ef9716ed0b63444ee7e48d3 Subproject commit 589e9960c0f6b0f96e4ba030ce8ed2d59ebf4f05

4
src/main/scala/unleashed/u500ml507devkit/Config.scala
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@ -14,7 +14,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.terminal._ import sifive.blocks.devices.terminal._
import sifive.freedom.unleashed.u500ml507devkit.fpga._ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
// Default FreedomUML507Config // Default FreedomUML507Config
class FreedomUML507Config extends Config( class FreedomUML507Config extends Config(
@ -46,7 +46,7 @@ class U500ML507DevKitConfig extends Config(
new FreedomUML507Config().alter((site,here,up) => { new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128) case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryML507Key => MemoryML507Params(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000) case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L) case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case JtagDTMKey => new JtagDTMConfig ( case JtagDTMKey => new JtagDTMConfig (

1
src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
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@ -42,6 +42,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
//--------------------------------------------------------------------- //---------------------------------------------------------------------
connectTerminal (dut) connectTerminal (dut)
connectDDRMemory(dut)
connectDebugJTAG(dut) connectDebugJTAG(dut)
connectSPI (dut) connectSPI (dut)
connectUART (dut) connectUART (dut)

5
src/main/scala/unleashed/u500ml507devkit/System.scala
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@ -15,7 +15,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.terminal._ import sifive.blocks.devices.terminal._
import sifive.freedom.unleashed.u500ml507devkit.fpga._ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
// U500ML507DevKitSystem // U500ML507DevKitSystem
@ -40,7 +40,8 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
with HasPeripheryUARTModuleImp with HasPeripheryUARTModuleImp
with HasPeripheryTerminalModuleImp with HasPeripheryTerminalModuleImp
with HasPeripherySPIModuleImp with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp { with HasPeripheryGPIOModuleImp
with HasMemoryML507ModuleImp {
// Reset vector is set to the location of the mask rom // Reset vector is set to the location of the mask rom
val maskROMParams = p(PeripheryMaskROMKey) val maskROMParams = p(PeripheryMaskROMKey)
global_reset_vector := maskROMParams(0).address.U global_reset_vector := maskROMParams(0).address.U