diff --git a/fpga-shells b/fpga-shells
index 79b53cf..589e996 160000
--- a/fpga-shells
+++ b/fpga-shells
@@ -1 +1 @@
-Subproject commit 79b53cf2ae2478f20ef9716ed0b63444ee7e48d3
+Subproject commit 589e9960c0f6b0f96e4ba030ce8ed2d59ebf4f05
diff --git a/src/main/scala/unleashed/u500ml507devkit/Config.scala b/src/main/scala/unleashed/u500ml507devkit/Config.scala
index 7e4f5eb..ffce8bc 100644
--- a/src/main/scala/unleashed/u500ml507devkit/Config.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/Config.scala
@@ -14,7 +14,7 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.terminal._
 
-import sifive.freedom.unleashed.u500ml507devkit.fpga._
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
 
 // Default FreedomUML507Config
 class FreedomUML507Config extends Config(
@@ -46,7 +46,7 @@ class U500ML507DevKitConfig extends Config(
   new FreedomUML507Config().alter((site,here,up) => {
     case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
     case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
-    case MemoryML507Key => MemoryML507Params(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
+    case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
     case DTSTimebase => BigInt(1000000)
     case ExtMem => up(ExtMem).copy(size = 0x40000000L)
     case JtagDTMKey => new JtagDTMConfig (
diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
index 4a4ca26..2bcb8bf 100644
--- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
@@ -42,6 +42,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
     //---------------------------------------------------------------------
 
     connectTerminal (dut)
+    connectDDRMemory(dut)
     connectDebugJTAG(dut)
     connectSPI      (dut)
     connectUART     (dut)
diff --git a/src/main/scala/unleashed/u500ml507devkit/System.scala b/src/main/scala/unleashed/u500ml507devkit/System.scala
index fe4316a..5310355 100644
--- a/src/main/scala/unleashed/u500ml507devkit/System.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/System.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.terminal._
 
-import sifive.freedom.unleashed.u500ml507devkit.fpga._
+import sifive.fpgashells.devices.xilinx.xilinxml507mig._
 
 //-------------------------------------------------------------------------
 // U500ML507DevKitSystem
@@ -40,7 +40,8 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
     with HasPeripheryUARTModuleImp
     with HasPeripheryTerminalModuleImp
     with HasPeripherySPIModuleImp
-    with HasPeripheryGPIOModuleImp {
+    with HasPeripheryGPIOModuleImp
+    with HasMemoryML507ModuleImp {
   // Reset vector is set to the location of the mask rom
   val maskROMParams = p(PeripheryMaskROMKey)
   global_reset_vector := maskROMParams(0).address.U