16 lines
248 B
Verilog
16 lines
248 B
Verilog
// See LICENSE file for license details.
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module PowerOnResetFPGAOnly(
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input clock,
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output reg power_on_reset
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);
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initial begin
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power_on_reset <= 1'b1;
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end
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always @(posedge clock) begin
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power_on_reset <= 1'b0;
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end
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endmodule
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