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fpga-shells/src/main/scala/devices/xilinx
Wesley W. Terpstra 8b0d7ec91a
TransferSizes: just because a device CAN do more does not mean it should (#15)
Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
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xilinxvc707mig TransferSizes: just because a device CAN do more does not mean it should (#15) 2017-12-10 00:42:11 -08:00
xilinxvc707pciex1 xilinxvc707pciex1: use new node-style API and abstract crossing (#13) 2017-10-28 12:27:24 -07:00