Klemens Schölhorn b49f5cfa78 Reduce crossing and queue depths to save space and ease timing		2018-05-14 20:07:01 +02:00
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XilinxML507MIG.scala	Reduce crossing and queue depths to save space and ease timing	2018-05-14 20:07:01 +02:00
XilinxML507MIGPeriphery.scala	Add XilinxML507MIG periphery and connect top level signals	2018-05-10 00:29:22 +02:00