494 lines
22 KiB
Scala
494 lines
22 KiB
Scala
// See LICENSE for license details.
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package sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.util.{ElaborationArtefacts}
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// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
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// Black Box
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// Signals named _exactly_ as per Vivado generated verilog
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// s : -{lock, cache, prot, qos}
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trait VC707AXIToPCIeX1IOSerial extends Bundle {
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//serial external pins
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val pci_exp_txp = Bool(OUTPUT)
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val pci_exp_txn = Bool(OUTPUT)
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val pci_exp_rxp = Bool(INPUT)
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val pci_exp_rxn = Bool(INPUT)
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}
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trait VC707AXIToPCIeX1IOClocksReset extends Bundle {
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//clock, reset, control
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val axi_aresetn = Bool(INPUT)
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val axi_aclk_out = Clock(OUTPUT)
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val axi_ctl_aclk_out = Clock(OUTPUT)
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val mmcm_lock = Bool(OUTPUT)
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}
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//scalastyle:off
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//turn off linter: blackbox name must match verilog module
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class vc707axi_to_pcie_x1() extends BlackBox
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{
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val io = new Bundle with VC707AXIToPCIeX1IOSerial
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with VC707AXIToPCIeX1IOClocksReset {
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//refclk
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val REFCLK = Bool(INPUT)
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//clock, reset, control
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val INTX_MSI_Request = Bool(INPUT)
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val INTX_MSI_Grant = Bool(OUTPUT)
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val MSI_enable = Bool(OUTPUT)
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val MSI_Vector_Num = Bits(INPUT,5)
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val MSI_Vector_Width = Bits(OUTPUT,3)
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//interrupt
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val interrupt_out = Bool(OUTPUT)
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//axi slave
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//-{lock, cache, prot, qos}
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//slave interface write address
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val s_axi_awid = Bits(INPUT,4)
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val s_axi_awaddr = Bits(INPUT,32)
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val s_axi_awregion = Bits(INPUT,4)
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val s_axi_awlen = Bits(INPUT,8)
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val s_axi_awsize = Bits(INPUT,3)
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val s_axi_awburst = Bits(INPUT,2)
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//val s_axi_awlock = Bool(INPUT)
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//val s_axi_awcache = Bits(INPUT,4)
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//val s_axi_awprot = Bits(INPUT,3)
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//val s_axi_awqos = Bits(INPUT,4)
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val s_axi_awvalid = Bool(INPUT)
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val s_axi_awready = Bool(OUTPUT)
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//slave interface write data
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val s_axi_wdata = Bits(INPUT,64)
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val s_axi_wstrb = Bits(INPUT,8)
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val s_axi_wlast = Bool(INPUT)
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val s_axi_wvalid = Bool(INPUT)
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val s_axi_wready = Bool(OUTPUT)
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//slave interface write response
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val s_axi_bready = Bool(INPUT)
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val s_axi_bid = Bits(OUTPUT,4)
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val s_axi_bresp = Bits(OUTPUT,2)
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val s_axi_bvalid = Bool(OUTPUT)
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//slave interface read address
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val s_axi_arid = Bits(INPUT,4)
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val s_axi_araddr = Bits(INPUT,32)
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val s_axi_arregion = Bits(INPUT,4)
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val s_axi_arlen = Bits(INPUT,8)
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val s_axi_arsize = Bits(INPUT,3)
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val s_axi_arburst = Bits(INPUT,2)
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//val s_axi_arlock = Bits(INPUT,1)
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//val s_axi_arcache = Bits(INPUT,4)
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//val s_axi_arprot = Bits(INPUT,3)
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//val s_axi_arqos = Bits(INPUT,4)
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val s_axi_arvalid = Bool(INPUT)
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val s_axi_arready = Bool(OUTPUT)
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//slave interface read data
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val s_axi_rready = Bool(INPUT)
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val s_axi_rid = Bits(OUTPUT,4)
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val s_axi_rdata = Bits(OUTPUT,64)
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val s_axi_rresp = Bits(OUTPUT,2)
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val s_axi_rlast = Bool(OUTPUT)
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val s_axi_rvalid = Bool(OUTPUT)
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//axi master
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//-{id,region,qos}
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//slave interface write address ports
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//val m_axi_awid = Bits(OUTPUT,4)
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val m_axi_awaddr = Bits(OUTPUT,32)
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//val m_axi_awregion = Bits(OUTPUT,4)
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val m_axi_awlen = Bits(OUTPUT,8)
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val m_axi_awsize = Bits(OUTPUT,3)
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val m_axi_awburst = Bits(OUTPUT,2)
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val m_axi_awlock = Bool(OUTPUT)
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val m_axi_awcache = Bits(OUTPUT,4)
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val m_axi_awprot = Bits(OUTPUT,3)
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//val m_axi_awqos = Bits(OUTPUT,4)
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val m_axi_awvalid = Bool(OUTPUT)
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val m_axi_awready = Bool(INPUT)
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//slave interface write data ports
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val m_axi_wdata = Bits(OUTPUT,64)
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val m_axi_wstrb = Bits(OUTPUT,8)
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val m_axi_wlast = Bool(OUTPUT)
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val m_axi_wvalid = Bool(OUTPUT)
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val m_axi_wready = Bool(INPUT)
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//slave interface write response ports
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val m_axi_bready = Bool(OUTPUT)
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//val m_axi_bid = Bits(INPUT,4)
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val m_axi_bresp = Bits(INPUT,2)
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val m_axi_bvalid = Bool(INPUT)
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//slave interface read address ports
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//val m_axi_arid = Bits(OUTPUT,4)
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val m_axi_araddr = Bits(OUTPUT,32)
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//val m_axi_arregion = Bits(OUTPUT,4)
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val m_axi_arlen = Bits(OUTPUT,8)
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val m_axi_arsize = Bits(OUTPUT,3)
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val m_axi_arburst = Bits(OUTPUT,2)
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val m_axi_arlock = Bits(OUTPUT,1)
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val m_axi_arcache = Bits(OUTPUT,4)
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val m_axi_arprot = Bits(OUTPUT,3)
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//val m_axi_arqos = Bits(OUTPUT,4)
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val m_axi_arvalid = Bool(OUTPUT)
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val m_axi_arready = Bool(INPUT)
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//slave interface read data ports
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val m_axi_rready = Bool(OUTPUT)
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//val m_axi_rid = Bits(INPUT,4)
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val m_axi_rdata = Bits(INPUT,64)
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val m_axi_rresp = Bits(INPUT,2)
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val m_axi_rlast = Bool(INPUT)
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val m_axi_rvalid = Bool(INPUT)
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//axi lite slave for control
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val s_axi_ctl_awaddr = Bits(INPUT,32)
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val s_axi_ctl_awvalid = Bool(INPUT)
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val s_axi_ctl_awready = Bool(OUTPUT)
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val s_axi_ctl_wdata = Bits(INPUT,32)
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val s_axi_ctl_wstrb = Bits(INPUT,4)
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val s_axi_ctl_wvalid = Bool(INPUT)
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val s_axi_ctl_wready = Bool(OUTPUT)
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val s_axi_ctl_bresp = Bits(OUTPUT,2)
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val s_axi_ctl_bvalid = Bool(OUTPUT)
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val s_axi_ctl_bready = Bool(INPUT)
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val s_axi_ctl_araddr = Bits(INPUT,32)
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val s_axi_ctl_arvalid = Bool(INPUT)
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val s_axi_ctl_arready = Bool(OUTPUT)
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val s_axi_ctl_rdata = Bits(OUTPUT,32)
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val s_axi_ctl_rresp = Bits(OUTPUT,2)
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val s_axi_ctl_rvalid = Bool(OUTPUT)
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val s_axi_ctl_rready = Bool(INPUT)
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}
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}
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//scalastyle:off
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//wrap vc707_axi_to_pcie_x1 black box in Nasti Bundles
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class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
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{
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val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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val intc = "pcie_intc"
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def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
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val extra = Map(
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"#address-cells" -> ofInt(3),
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"#size-cells" -> ofInt(2),
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"#interrupt-cells" -> ofInt(1),
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"device_type" -> Seq(ResourceString("pci")),
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"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
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"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
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"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
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ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
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"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
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"interrupt-controller" -> Nil,
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"#address-cells" -> ofInt(0),
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"#interrupt-cells" -> ofInt(1)))))
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Description(name, mapping ++ extra)
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}
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}
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val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(0x60000000L, 0x1fffffffL)),
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resources = Seq(Resource(device, "ranges")),
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executable = true,
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supportsWrite = TransferSizes(1, 256),
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supportsRead = TransferSizes(1, 256))),
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beatBytes = 8)))
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val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(0x50000000L, 0x03ffffffL)),
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resources = device.reg("control"),
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supportsWrite = TransferSizes(1, 4),
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supportsRead = TransferSizes(1, 4),
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interleavedId = Some(0))), // AXI4-Lite never interleaves responses
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beatBytes = 4)))
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val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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name = "VC707 PCIe",
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id = IdRange(0, 1),
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aligned = false)))))
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val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
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lazy val module = new LazyModuleImp(this) {
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// The master on the control port must be AXI-lite
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require (control.edgesIn(0).master.endId == 1)
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// Must have exactly the right number of idBits
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require (slave.edgesIn(0).bundle.idBits == 4)
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class VC707AXIToPCIeX1IOBundle extends Bundle with VC707AXIToPCIeX1IOSerial
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with VC707AXIToPCIeX1IOClocksReset;
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val io = new Bundle {
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val port = new VC707AXIToPCIeX1IOBundle
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val slave_in = slave.bundleIn
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val control_in = control.bundleIn
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val master_out = master.bundleOut
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val REFCLK = Bool(INPUT)
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val interrupt_out = intnode.bundleOut
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}
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val blackbox = Module(new vc707axi_to_pcie_x1)
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val s = io.slave_in(0)
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val c = io.control_in(0)
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val m = io.master_out(0)
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//to top level
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blackbox.io.axi_aresetn := io.port.axi_aresetn
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io.port.axi_aclk_out := blackbox.io.axi_aclk_out
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io.port.axi_ctl_aclk_out := blackbox.io.axi_ctl_aclk_out
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io.port.mmcm_lock := blackbox.io.mmcm_lock
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io.port.pci_exp_txp := blackbox.io.pci_exp_txp
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io.port.pci_exp_txn := blackbox.io.pci_exp_txn
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blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp
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blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn
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io.interrupt_out(0)(0) := blackbox.io.interrupt_out
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blackbox.io.REFCLK := io.REFCLK
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//s
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//AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2
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//-{lock, cache, prot, qos}
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//-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
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//global signals
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//aclk :=
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//aresetn :=
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//slave interface write address
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blackbox.io.s_axi_awid := s.aw.bits.id
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blackbox.io.s_axi_awaddr := s.aw.bits.addr
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blackbox.io.s_axi_awlen := s.aw.bits.len
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blackbox.io.s_axi_awsize := s.aw.bits.size
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blackbox.io.s_axi_awburst := s.aw.bits.burst
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//blackbox.io.s_axi_awlock := s.aw.bits.lock
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//blackbox.io.s_axi_awcache := s.aw.bits.cache
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//blackbox.io.s_axi_awprot := s.aw.bits.prot
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//blackbox.io.s_axi_awqos := s.aw.bits.qos
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blackbox.io.s_axi_awregion := UInt(0)
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//blackbox.io.awuser := s.aw.bits.user
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blackbox.io.s_axi_awvalid := s.aw.valid
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s.aw.ready := blackbox.io.s_axi_awready
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//slave interface write data ports
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//blackbox.io.s_axi_wid := s.w.bits.id
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blackbox.io.s_axi_wdata := s.w.bits.data
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blackbox.io.s_axi_wstrb := s.w.bits.strb
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blackbox.io.s_axi_wlast := s.w.bits.last
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//blackbox.io.s_axi_wuser := s.w.bits.user
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blackbox.io.s_axi_wvalid := s.w.valid
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s.w.ready := blackbox.io.s_axi_wready
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//slave interface write response
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s.b.bits.id := blackbox.io.s_axi_bid
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s.b.bits.resp := blackbox.io.s_axi_bresp
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//s.b.bits.user := blackbox.io.s_axi_buser
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s.b.valid := blackbox.io.s_axi_bvalid
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blackbox.io.s_axi_bready := s.b.ready
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//slave AXI interface read address ports
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blackbox.io.s_axi_arid := s.ar.bits.id
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blackbox.io.s_axi_araddr := s.ar.bits.addr
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blackbox.io.s_axi_arlen := s.ar.bits.len
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blackbox.io.s_axi_arsize := s.ar.bits.size
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blackbox.io.s_axi_arburst := s.ar.bits.burst
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//blackbox.io.s_axi_arlock := s.ar.bits.lock
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//blackbox.io.s_axi_arcache := s.ar.bits.cache
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//blackbox.io.s_axi_arprot := s.ar.bits.prot
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//blackbox.io.s_axi_arqos := s.ar.bits.qos
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blackbox.io.s_axi_arregion := UInt(0)
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//blackbox.io.s_axi_aruser := s.ar.bits.user
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blackbox.io.s_axi_arvalid := s.ar.valid
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s.ar.ready := blackbox.io.s_axi_arready
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//slave AXI interface read data ports
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s.r.bits.id := blackbox.io.s_axi_rid
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s.r.bits.data := blackbox.io.s_axi_rdata
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s.r.bits.resp := blackbox.io.s_axi_rresp
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s.r.bits.last := blackbox.io.s_axi_rlast
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//s.r.bits.ruser := blackbox.io.s_axi_ruser
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s.r.valid := blackbox.io.s_axi_rvalid
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blackbox.io.s_axi_rready := s.r.ready
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//ctl
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//axi-lite slave interface write address
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blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr
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blackbox.io.s_axi_ctl_awvalid := c.aw.valid
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c.aw.ready := blackbox.io.s_axi_ctl_awready
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//axi-lite slave interface write data ports
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blackbox.io.s_axi_ctl_wdata := c.w.bits.data
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blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb
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blackbox.io.s_axi_ctl_wvalid := c.w.valid
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c.w.ready := blackbox.io.s_axi_ctl_wready
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//axi-lite slave interface write response
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blackbox.io.s_axi_ctl_bready := c.b.ready
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c.b.bits.id := UInt(0)
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c.b.bits.resp := blackbox.io.s_axi_ctl_bresp
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c.b.valid := blackbox.io.s_axi_ctl_bvalid
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//axi-lite slave AXI interface read address ports
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blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr
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blackbox.io.s_axi_ctl_arvalid := c.ar.valid
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c.ar.ready := blackbox.io.s_axi_ctl_arready
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//slave AXI interface read data ports
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blackbox.io.s_axi_ctl_rready := c.r.ready
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c.r.bits.id := UInt(0)
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c.r.bits.data := blackbox.io.s_axi_ctl_rdata
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c.r.bits.resp := blackbox.io.s_axi_ctl_rresp
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c.r.bits.last := Bool(true)
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c.r.valid := blackbox.io.s_axi_ctl_rvalid
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//m
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//AXI4 signals ordered per AXI4 Specification (Release D) Section A.2
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//-{id,region,qos}
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//-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
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//global signals
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//aclk :=
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//aresetn :=
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//master interface write address
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m.aw.bits.id := UInt(0)
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m.aw.bits.addr := blackbox.io.m_axi_awaddr
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m.aw.bits.len := blackbox.io.m_axi_awlen
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m.aw.bits.size := blackbox.io.m_axi_awsize
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m.aw.bits.burst := blackbox.io.m_axi_awburst
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m.aw.bits.lock := blackbox.io.m_axi_awlock
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m.aw.bits.cache := blackbox.io.m_axi_awcache
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m.aw.bits.prot := blackbox.io.m_axi_awprot
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m.aw.bits.qos := UInt(0)
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//m.aw.bits.region := blackbox.io.m_axi_awregion
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//m.aw.bits.user := blackbox.io.m_axi_awuser
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m.aw.valid := blackbox.io.m_axi_awvalid
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blackbox.io.m_axi_awready := m.aw.ready
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//master interface write data ports
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m.w.bits.data := blackbox.io.m_axi_wdata
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m.w.bits.strb := blackbox.io.m_axi_wstrb
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m.w.bits.last := blackbox.io.m_axi_wlast
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//m.w.bits.user := blackbox.io.m_axi_wuser
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m.w.valid := blackbox.io.m_axi_wvalid
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blackbox.io.m_axi_wready := m.w.ready
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//master interface write response
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//blackbox.io.m_axi_bid := m.b.bits.id
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blackbox.io.m_axi_bresp := m.b.bits.resp
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//blackbox.io.m_axi_buser := m.b.bits.user
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blackbox.io.m_axi_bvalid := m.b.valid
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m.b.ready := blackbox.io.m_axi_bready
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//master AXI interface read address ports
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m.ar.bits.id := UInt(0)
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m.ar.bits.addr := blackbox.io.m_axi_araddr
|
|
m.ar.bits.len := blackbox.io.m_axi_arlen
|
|
m.ar.bits.size := blackbox.io.m_axi_arsize
|
|
m.ar.bits.burst := blackbox.io.m_axi_arburst
|
|
m.ar.bits.lock := blackbox.io.m_axi_arlock
|
|
m.ar.bits.cache := blackbox.io.m_axi_arcache
|
|
m.ar.bits.prot := blackbox.io.m_axi_arprot
|
|
m.ar.bits.qos := UInt(0)
|
|
//m.ar.bits.region := blackbox.io.m_axi_arregion
|
|
//m.ar.bits.user := blackbox.io.s_axi_aruser
|
|
m.ar.valid := blackbox.io.m_axi_arvalid
|
|
blackbox.io.m_axi_arready := m.ar.ready
|
|
|
|
//master AXI interface read data ports
|
|
//blackbox.io.m_axi_rid := m.r.bits.id
|
|
blackbox.io.m_axi_rdata := m.r.bits.data
|
|
blackbox.io.m_axi_rresp := m.r.bits.resp
|
|
blackbox.io.m_axi_rlast := m.r.bits.last
|
|
//blackbox.io.s_axi_ruser := s.bits.ruser
|
|
blackbox.io.m_axi_rvalid := m.r.valid
|
|
m.r.ready := blackbox.io.m_axi_rready
|
|
}
|
|
|
|
ElaborationArtefacts.add(
|
|
"vc707axi_to_pcie_x1.vivado.tcl",
|
|
"""
|
|
create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
|
|
set_property -dict [list \
|
|
CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
|
|
CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
|
|
CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
|
|
CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
|
|
CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
|
|
CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
|
|
CONFIG.AXIBAR_0 {0x60000000} \
|
|
CONFIG.AXIBAR_1 {0xFFFFFFFF} \
|
|
CONFIG.AXIBAR_2 {0xFFFFFFFF} \
|
|
CONFIG.AXIBAR_3 {0xFFFFFFFF} \
|
|
CONFIG.AXIBAR_4 {0xFFFFFFFF} \
|
|
CONFIG.AXIBAR_5 {0xFFFFFFFF} \
|
|
CONFIG.AXIBAR_AS_0 {true} \
|
|
CONFIG.AXIBAR_AS_1 {false} \
|
|
CONFIG.AXIBAR_AS_2 {false} \
|
|
CONFIG.AXIBAR_AS_3 {false} \
|
|
CONFIG.AXIBAR_AS_4 {false} \
|
|
CONFIG.AXIBAR_AS_5 {false} \
|
|
CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
|
|
CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
|
|
CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
|
|
CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
|
|
CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \
|
|
CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \
|
|
CONFIG.AXIBAR_NUM {1} \
|
|
CONFIG.BAR0_ENABLED {true} \
|
|
CONFIG.BAR0_SCALE {Gigabytes} \
|
|
CONFIG.BAR0_SIZE {4} \
|
|
CONFIG.BAR0_TYPE {Memory} \
|
|
CONFIG.BAR1_ENABLED {false} \
|
|
CONFIG.BAR1_SCALE {N/A} \
|
|
CONFIG.BAR1_SIZE {8} \
|
|
CONFIG.BAR1_TYPE {N/A} \
|
|
CONFIG.BAR2_ENABLED {false} \
|
|
CONFIG.BAR2_SCALE {N/A} \
|
|
CONFIG.BAR2_SIZE {8} \
|
|
CONFIG.BAR2_TYPE {N/A} \
|
|
CONFIG.BAR_64BIT {true} \
|
|
CONFIG.BASEADDR {0x50000000} \
|
|
CONFIG.BASE_CLASS_MENU {Bridge_device} \
|
|
CONFIG.CLASS_CODE {0x060400} \
|
|
CONFIG.COMP_TIMEOUT {50ms} \
|
|
CONFIG.Component_Name {design_1_axi_pcie_1_0} \
|
|
CONFIG.DEVICE_ID {0x7111} \
|
|
CONFIG.ENABLE_CLASS_CODE {true} \
|
|
CONFIG.HIGHADDR {0x53FFFFFF} \
|
|
CONFIG.INCLUDE_BAROFFSET_REG {true} \
|
|
CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
|
|
CONFIG.INTERRUPT_PIN {false} \
|
|
CONFIG.MAX_LINK_SPEED {2.5_GT/s} \
|
|
CONFIG.MSI_DECODE_ENABLED {true} \
|
|
CONFIG.M_AXI_ADDR_WIDTH {32} \
|
|
CONFIG.M_AXI_DATA_WIDTH {64} \
|
|
CONFIG.NO_OF_LANES {X1} \
|
|
CONFIG.NUM_MSI_REQ {0} \
|
|
CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \
|
|
CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \
|
|
CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \
|
|
CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \
|
|
CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \
|
|
CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \
|
|
CONFIG.PCIE_BLK_LOCN {X1Y1} \
|
|
CONFIG.PCIE_USE_MODE {GES_and_Production} \
|
|
CONFIG.REF_CLK_FREQ {100_MHz} \
|
|
CONFIG.REV_ID {0x00} \
|
|
CONFIG.SLOT_CLOCK_CONFIG {true} \
|
|
CONFIG.SUBSYSTEM_ID {0x0007} \
|
|
CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \
|
|
CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \
|
|
CONFIG.S_AXI_ADDR_WIDTH {32} \
|
|
CONFIG.S_AXI_DATA_WIDTH {64} \
|
|
CONFIG.S_AXI_ID_WIDTH {4} \
|
|
CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \
|
|
CONFIG.VENDOR_ID {0x10EE} \
|
|
CONFIG.XLNX_REF_BOARD {None} \
|
|
CONFIG.axi_aclk_loopback {false} \
|
|
CONFIG.en_ext_ch_gt_drp {false} \
|
|
CONFIG.en_ext_clk {false} \
|
|
CONFIG.en_ext_gt_common {false} \
|
|
CONFIG.en_ext_pipe_interface {false} \
|
|
CONFIG.en_transceiver_status_ports {false} \
|
|
CONFIG.no_slv_err {false} \
|
|
CONFIG.rp_bar_hide {true} \
|
|
CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]"""
|
|
)
|
|
}
|