67 lines
1.9 KiB
Tcl
67 lines
1.9 KiB
Tcl
# See LICENSE for license details.
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# Set the variable for the directory that includes all scripts
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set scriptdir [file dirname [info script]]
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# Set the variable for all the common files
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set commondir [file dirname $scriptdir]
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# Set the variable that points to board specific files
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set boarddir [file join [file dirname $commondir] $name]
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# Set the variable that points to board constraint files
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set constraintsdir [file join $boarddir constraints]
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# Set the variable that points to common verilog sources
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set srcdir [file join $commondir vsrc]
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# Creates a work directory
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set wrkdir [file join [pwd] obj]
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# Create the directory for IPs
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set ipdir [file join $wrkdir ip]
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# Set the top for the design based on an environment variable
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set top $::env(FPGA_TOP_SYSTEM)
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# Create an in-memory project
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create_project -part $part_fpga -in_memory
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# Set the board part, target language, default library, and IP directory
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# paths for the current project
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set_property -dict [list \
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BOARD_PART $part_board \
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TARGET_LANGUAGE {Verilog} \
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DEFAULT_LIB {xil_defaultlib} \
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IP_REPO_PATHS $ipdir \
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] [current_project]
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if {[get_filesets -quiet sources_1] eq ""} {
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create_fileset -srcset sources_1
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}
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set obj [current_fileset]
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# Add verilog files TCL from VSRCSVIVADOTCL environment variable
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if {[info exists ::env(VSRCSVIVADOTCL)]} {
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source $::env(VSRCSVIVADOTCL)
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}
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# Add IP Vivado TCL from IPVIVADOTCL environment variable
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if {[info exists ::env(IPVIVADOTCLS)]} {
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# Split string into words even with multiple consecutive spaces
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# http://wiki.tcl.tk/989
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set ipvivadotcls [regexp -inline -all -- {\S+} $::env(IPVIVADOTCLS)]
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}
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if {[get_filesets -quiet sim_1] eq ""} {
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create_fileset -simset sim_1
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}
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set obj [current_fileset -simset]
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if {[get_filesets -quiet constrs_1] eq ""} {
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create_fileset -constrset constrs_1
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}
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set obj [current_fileset -constrset]
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add_files -norecurse -fileset $obj [glob -directory $constraintsdir {*.xdc}]
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