riscv/fpga-shells
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base: riscv:e9625bf8ee21c467a8bb6df3f9304c17411c93b6
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riscv:ml507
riscv:master
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compare: riscv:2ff28e6af695cecfa089da1ee26288517656c81d
Branches Tags
riscv:ml507
riscv:master

2 Commits
e9625bf8ee ... 2ff28e6af6

Author SHA1 Message Date
Klemens Schölhorn
2ff28e6af6 Add status indication led for the reset button 2018-04-18 00:26:43 +02:00
Klemens Schölhorn
41362a1cb5 Remove unused UART signals (rs and cs) from ml507 2018-04-18 00:26:00 +02:00
1 changed files with 4 additions and 4 deletions
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src/main/scala/shell/xilinx/ML507Shell.scala
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@ -98,6 +98,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// active high reset // active high reset
val reset = IO(Input(Bool())) val reset = IO(Input(Bool()))
val reset_led = IO(Output(Bool()))
// LED // LED
val led = IO(Vec(8, Output(Bool()))) val led = IO(Vec(8, Output(Bool())))
@ -105,8 +106,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART // UART
val uart_tx = IO(Output(Bool())) val uart_tx = IO(Output(Bool()))
val uart_rx = IO(Input(Bool())) val uart_rx = IO(Input(Bool()))
val uart_rtsn = IO(Output(Bool()))
val uart_ctsn = IO(Input(Bool()))
// SDIO // SDIO
val sdio_clk = IO(Output(Bool())) val sdio_clk = IO(Output(Bool()))
@ -176,6 +175,9 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// Allow the debug module to reset everything. Resets the MIG // Allow the debug module to reset everything. Resets the MIG
sys_reset := reset | dut_ndreset sys_reset := reset | dut_ndreset
// Status LED for reset
reset_led := reset
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
// Clock Generator // Clock Generator
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
@ -225,8 +227,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART // UART
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
uart_rtsn := false.B
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey) val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) { if (!uartParams.isEmpty) {