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synchronizers: decided that ShiftRegInit should be reversed as the others.

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Megan Wachs 2017-09-07 09:54:35 -07:00
parent fd70d118d3
commit cab572fab2
1 changed files with 1 additions and 1 deletions
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xilinx/vc707/constraints/vc707-master.xdc
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@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
# Platform specific constraints
set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
set_property IOB TRUE [get_cells "uart_rxd_sync/sync_0"]
set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"]
# PCI Express
#FMC 1 refclk