From cab572fab2bd35a11ba90d94dfce6325d37ac241 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 7 Sep 2017 09:54:35 -0700 Subject: [PATCH] synchronizers: decided that ShiftRegInit should be reversed as the others. --- xilinx/vc707/constraints/vc707-master.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc index f6b11a7..5774ffc 100644 --- a/xilinx/vc707/constraints/vc707-master.xdc +++ b/xilinx/vc707/constraints/vc707-master.xdc @@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn] # Platform specific constraints set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"] -set_property IOB TRUE [get_cells "uart_rxd_sync/sync_0"] +set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"] # PCI Express #FMC 1 refclk