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vc707: Updates to the constraints and shell

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This commit is contained in:
Shreesha Srinath 2017-08-17 18:51:01 -07:00
parent ab8cf0775f
commit c58e79f155
2 changed files with 6 additions and 10 deletions
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9
src/main/scala/shell/xilinx/VC707Shell.scala
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@ -11,6 +11,7 @@ import freechips.rocketchip.devices.debug._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.util.{ShiftRegister}
import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
@ -201,14 +202,10 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {
// synchronize uart_rx
val uart_rx_sync_reg0 = RegInit(true.B)
uart_rx_sync_reg0 := uart_rx
val uart_rx_sync_reg1 = RegInit(true.B)
uart_rx_sync_reg1 := uart_rx_sync_reg0
val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx"))
// uart connections
dut.uart(0).rxd := uart_rx_sync_reg1
dut.uart(0).rxd := uart_rx_sync
uart_tx := dut.uart(0).txd
}
}

7
xilinx/vc707/constraints/vc707-master.xdc
View File

@ -29,10 +29,9 @@ set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
set_property IOB TRUE [get_ports uart_rtsn]
# FIXME: shreesha: I need to see if these matter and add them back
# currently everything works without it....
#set_property IOB TRUE [get_cells "top/RocketChipTop/uarts_0/txm/out_reg"]
#set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
# Platform specific constraints
set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
set_property IOB TRUE [get_cells "uart_rx_sync_0"]
# PCI Express
#FMC 1 refclk