diff --git a/src/main/scala/shell/xilinx/VC707Shell.scala b/src/main/scala/shell/xilinx/VC707Shell.scala
index c87c357..d11f7a8 100644
--- a/src/main/scala/shell/xilinx/VC707Shell.scala
+++ b/src/main/scala/shell/xilinx/VC707Shell.scala
@@ -11,6 +11,7 @@ import freechips.rocketchip.devices.debug._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
+import sifive.blocks.util.{ShiftRegister}
 
 import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
@@ -201,14 +202,10 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
     val uartParams = p(PeripheryUARTKey)
     if (!uartParams.isEmpty) {
       // synchronize uart_rx
-      val uart_rx_sync_reg0 = RegInit(true.B)
-      uart_rx_sync_reg0 := uart_rx
-
-      val uart_rx_sync_reg1 = RegInit(true.B)
-      uart_rx_sync_reg1 := uart_rx_sync_reg0
+      val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx"))
 
       // uart connections
-      dut.uart(0).rxd := uart_rx_sync_reg1
+      dut.uart(0).rxd := uart_rx_sync
       uart_tx         := dut.uart(0).txd
     }
   }
diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc
index d5b4fff..608a358 100644
--- a/xilinx/vc707/constraints/vc707-master.xdc
+++ b/xilinx/vc707/constraints/vc707-master.xdc
@@ -29,10 +29,9 @@ set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
 set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
 set_property IOB TRUE [get_ports uart_rtsn]
 
-# FIXME: shreesha: I need to see if these matter and add them back
-# currently everything works without it....
-#set_property IOB TRUE [get_cells "top/RocketChipTop/uarts_0/txm/out_reg"]
-#set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
+# Platform specific constraints
+set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
+set_property IOB TRUE [get_cells "uart_rx_sync_0"]
 
 # PCI Express
 #FMC 1 refclk