vc707: Updates to the constraints and shell
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@ -11,6 +11,7 @@ import freechips.rocketchip.devices.debug._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.uart._
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import sifive.blocks.util.{ShiftRegister}
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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@ -201,14 +202,10 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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val uartParams = p(PeripheryUARTKey)
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val uartParams = p(PeripheryUARTKey)
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if (!uartParams.isEmpty) {
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if (!uartParams.isEmpty) {
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// synchronize uart_rx
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// synchronize uart_rx
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val uart_rx_sync_reg0 = RegInit(true.B)
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val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx"))
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uart_rx_sync_reg0 := uart_rx
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val uart_rx_sync_reg1 = RegInit(true.B)
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uart_rx_sync_reg1 := uart_rx_sync_reg0
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// uart connections
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// uart connections
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dut.uart(0).rxd := uart_rx_sync_reg1
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dut.uart(0).rxd := uart_rx_sync
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uart_tx := dut.uart(0).txd
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uart_tx := dut.uart(0).txd
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}
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}
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}
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}
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@ -29,10 +29,9 @@ set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
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set_property IOB TRUE [get_ports uart_rtsn]
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set_property IOB TRUE [get_ports uart_rtsn]
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# FIXME: shreesha: I need to see if these matter and add them back
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# Platform specific constraints
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# currently everything works without it....
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set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
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#set_property IOB TRUE [get_cells "top/RocketChipTop/uarts_0/txm/out_reg"]
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set_property IOB TRUE [get_cells "uart_rx_sync_0"]
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#set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
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# PCI Express
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# PCI Express
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#FMC 1 refclk
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#FMC 1 refclk
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