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VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals

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This commit is contained in:
Henry Styles
2017-10-23 16:53:59 -07:00
parent d8e50c7646
commit 61b167e8d9
2 changed files with 13 additions and 48 deletions
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12
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@@ -10,14 +10,20 @@ import freechips.rocketchip.tilelink._
import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
trait VC707AXIToPCIeRefClk extends Bundle{
val REFCLK_rxp = Bool(INPUT)
val REFCLK_rxn = Bool(INPUT)
}
class XilinxVC707PCIeX1Pads extends Bundle
with VC707AXIToPCIeX1IOSerial
with VC707AXIToPCIeRefClk
class XilinxVC707PCIeX1IO extends Bundle
with VC707AXIToPCIeRefClk
with VC707AXIToPCIeX1IOSerial
with VC707AXIToPCIeX1IOClocksReset {
val axi_ctl_aresetn = Bool(INPUT)
val REFCLK_rxp = Bool(INPUT)
val REFCLK_rxn = Bool(INPUT)
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {