Generate separate processor and terminal clocks

src/main/scala/ip/xilinx/Xilinx.scala

@@ -94,10 +94,21 @@ object PowerOnResetFPGAOnly {
   }
 }
 
-// ML507 clock generation
+//-------------------------------------------------------------------------
+// ml507 clocks (DCM_ADV)
+//-------------------------------------------------------------------------
+
 class ml507_sys_clock extends BlackBox {
   val io = new Bundle {
-    val CLKIN_IN  = Bool(INPUT)
+    val CLKIN_IN  = Clock(INPUT)
+    val CLKFX_OUT = Clock(OUTPUT)
+    val LOCKED_OUT = Bool(OUTPUT)
+  }
+}
+
+class ml507_dvi_clock extends BlackBox {
+  val io = new Bundle {
+    val CLKIN_IN  = Clock(INPUT)
     val CLKFX_OUT = Clock(OUTPUT)
     val LOCKED_OUT = Bool(OUTPUT)
   }