From 5bcc4e82fdc65bcd25c92e4f11a9c8421bacdea8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= <klemens@schoelhorn.eu>
Date: Mon, 30 Apr 2018 22:52:02 +0200
Subject: [PATCH] Generate separate processor and terminal clocks

---
 src/main/scala/ip/xilinx/Xilinx.scala        | 15 +++++-
 src/main/scala/shell/xilinx/ML507Shell.scala | 48 +++++++++++---------
 2 files changed, 39 insertions(+), 24 deletions(-)

diff --git a/src/main/scala/ip/xilinx/Xilinx.scala b/src/main/scala/ip/xilinx/Xilinx.scala
index 0d6c4ec..6355bee 100644
--- a/src/main/scala/ip/xilinx/Xilinx.scala
+++ b/src/main/scala/ip/xilinx/Xilinx.scala
@@ -94,10 +94,21 @@ object PowerOnResetFPGAOnly {
   }
 }
 
-// ML507 clock generation
+//-------------------------------------------------------------------------
+// ml507 clocks (DCM_ADV)
+//-------------------------------------------------------------------------
+
 class ml507_sys_clock extends BlackBox {
   val io = new Bundle {
-    val CLKIN_IN  = Bool(INPUT)
+    val CLKIN_IN  = Clock(INPUT)
+    val CLKFX_OUT = Clock(OUTPUT)
+    val LOCKED_OUT = Bool(OUTPUT)
+  }
+}
+
+class ml507_dvi_clock extends BlackBox {
+  val io = new Bundle {
+    val CLKIN_IN  = Clock(INPUT)
     val CLKFX_OUT = Clock(OUTPUT)
     val LOCKED_OUT = Bool(OUTPUT)
   }
diff --git a/src/main/scala/shell/xilinx/ML507Shell.scala b/src/main/scala/shell/xilinx/ML507Shell.scala
index 02ed228..ca1e3e6 100644
--- a/src/main/scala/shell/xilinx/ML507Shell.scala
+++ b/src/main/scala/shell/xilinx/ML507Shell.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart._
 import sifive.blocks.devices.chiplink._
 import sifive.blocks.devices.terminal._
 
-import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_sys_clock , vc707reset}
+import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_dvi_clock, ml507_sys_clock, vc707reset}
 
 //-------------------------------------------------------------------------
 // ML507Shell
@@ -54,9 +54,9 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   //-----------------------------------------------------------------------
 
   // 100Mhz sysclk
-  val sys_clock_100        = IO(Input(Bool()))
+  val sys_clock            = IO(Input(Clock()))
 
-  // active high reset
+  // active high async reset
   val reset                = IO(Input(Bool()))
 
   // LED
@@ -97,46 +97,49 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // Wire declrations
   //-----------------------------------------------------------------------
 
-  val sys_clock       = Wire(Clock())
+  // async resets
   val sys_reset       = Wire(Bool())
+  val do_reset        = Wire(Bool())
+  val dut_ndreset     = Wire(Bool())
 
   val dut_clock       = Wire(Clock())
   val dut_reset       = Wire(Bool())
 
-  val dut_ndreset     = Wire(Bool())
+  val dvi_clock       = Wire(Clock())
+  val dvi_reset       = Wire(Bool())
 
   val sd_spi_sck      = Wire(Bool())
   val sd_spi_cs       = Wire(Bool())
   val sd_spi_dq_i     = Wire(Vec(4, Bool()))
   val sd_spi_dq_o     = Wire(Vec(4, Bool()))
 
-  val do_reset        = Wire(Bool())
-
   val clk_locked      = Wire(Bool())
 
 
   //-----------------------------------------------------------------------
-  // System clock and reset
+  // System reset
   //-----------------------------------------------------------------------
 
-  // Clock that drives the clock generator and the MIG
-  sys_clock := sys_clock_100.asClock()
-
   // Allow the debug module to reset everything. Resets the MIG
   sys_reset := reset | dut_ndreset
 
   //-----------------------------------------------------------------------
-  // Clock Generator
+  // Clock generators
   //-----------------------------------------------------------------------
 
-  // 48 MHz (TMP, normally 50 MHz)
+  // 80 MHz (processor clock)
   val ml507_sys_clock = Module(new ml507_sys_clock)
-  ml507_sys_clock.io.CLKIN_IN := sys_clock.asUInt
-  val clk50 = ml507_sys_clock.io.CLKFX_OUT
-  clk_locked := ml507_sys_clock.io.LOCKED_OUT
+  ml507_sys_clock.io.CLKIN_IN := sys_clock
+  dut_clock := ml507_sys_clock.io.CLKFX_OUT
 
-  // DUT clock
-  dut_clock := clk50
+  // 48 MHz (DVI pixel clock for SDR 640x480x60)
+  val ml507_dvi_clock = Module(new ml507_dvi_clock)
+  ml507_dvi_clock.io.CLKIN_IN := sys_clock
+  dvi_clock := ml507_dvi_clock.io.CLKFX_OUT
+
+  // Clocks locked?
+  clk_locked := ml507_sys_clock.io.LOCKED_OUT &
+                ml507_dvi_clock.io.LOCKED_OUT
 
   //-----------------------------------------------------------------------
   // System reset
@@ -144,13 +147,14 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
 
   do_reset             := !clk_locked || sys_reset
 
-  // TODO: adapt for ml507?
+  // synchronize async resets
   val safe_reset = Module(new vc707reset)
 
   safe_reset.io.areset := do_reset
   safe_reset.io.clock1 := dut_clock
   safe_reset.io.clock2 := dut_clock
-  safe_reset.io.clock3 := dut_clock
+  safe_reset.io.clock3 := dvi_clock
+  dvi_reset            := safe_reset.io.reset3
   safe_reset.io.clock4 := dut_clock
   dut_reset            := safe_reset.io.reset4
 
@@ -164,8 +168,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
 
   def connectTerminal(dut: HasPeripheryTerminalModuleImp): Unit = {
     dvi <> dut.dvi
-    dut.terminal.clk := dut_clock
-    dut.terminal.reset := dut_reset
+    dut.terminal.clk := dvi_clock
+    dut.terminal.reset := dvi_reset
   }
 
   //-----------------------------------------------------------------------