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diplomacy: update to new API (#7)

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This commit is contained in:
Wesley W. Terpstra
2017-09-27 16:32:43 -07:00
committed by GitHub
parent 32d4083890
commit 4af0552374
5 changed files with 26 additions and 35 deletions
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16
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -21,10 +21,10 @@ class XilinxVC707PCIeX1IO extends Bundle
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLAsyncInputNode()
val control = TLAsyncInputNode()
val master = TLAsyncOutputNode()
val intnode = IntOutputNode()
val slave = TLAsyncIdentityNode()
val control = TLAsyncIdentityNode()
val master = TLAsyncIdentityNode()
val intnode = IntIdentityNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@ -56,13 +56,9 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val port = new XilinxVC707PCIeX1IO
val slave_in = slave.bundleIn
val control_in = control.bundleIn
val master_out = master.bundleOut
val interrupt = intnode.bundleOut
}
})
io.port <> axi_to_pcie_x1.module.io.port