diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala index 1280b3e..fe093de 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala @@ -30,8 +30,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton") val device = new MemoryDevice - val node = TLInputNode() - val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( + val axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = c.address, resources = device.reg, @@ -48,8 +47,8 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L val yank = LazyModule(new AXI4UserYanker) val buffer = LazyModule(new AXI4Buffer) - xing.node := node - val monitor = (toaxi4.node := xing.node) + val node: TLInwardNode = xing.node + toaxi4.node := xing.node axi4 := buffer.node buffer.node := yank.node yank.node := deint.node @@ -57,10 +56,9 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L indexer.node := toaxi4.node lazy val module = new LazyModuleImp(this) { - val io = new Bundle { + val io = IO(new Bundle { val port = new XilinxVC707MIGIO(depth) - val tl = node.bundleIn - } + }) //MIG black box instantiation val blackbox = Module(new vc707mig(depth)) @@ -91,12 +89,12 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L blackbox.io.sys_clk_i := io.port.sys_clk_i //user interface signals - val axi_async = axi4.bundleIn(0) + val (axi_async, _) = axi4.in(0) xing.module.io.in_clock := clock xing.module.io.in_reset := reset xing.module.io.out_clock := blackbox.io.ui_clk xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst - (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm => + Seq(toaxi4, indexer, deint, yank, buffer) foreach { lm => lm.module.clock := blackbox.io.ui_clk lm.module.reset := blackbox.io.ui_clk_sync_rst } diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index 667c659..734d973 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -4,7 +4,7 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707mig import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.HasMemoryBus -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange} case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] @@ -24,7 +24,7 @@ trait HasMemoryXilinxVC707MIGBundle { } } -trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp +trait HasMemoryXilinxVC707MIGModuleImp extends LazyModuleImp with HasMemoryXilinxVC707MIGBundle { val outer: HasMemoryXilinxVC707MIG val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) diff --git a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala index 5d88d29..1dbea70 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala @@ -21,10 +21,10 @@ class XilinxVC707PCIeX1IO extends Bundle } class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { - val slave = TLAsyncInputNode() - val control = TLAsyncInputNode() - val master = TLAsyncOutputNode() - val intnode = IntOutputNode() + val slave = TLAsyncIdentityNode() + val control = TLAsyncIdentityNode() + val master = TLAsyncIdentityNode() + val intnode = IntIdentityNode() val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) @@ -56,13 +56,9 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { intnode := axi_to_pcie_x1.intnode lazy val module = new LazyModuleImp(this) { - val io = new Bundle { + val io = IO(new Bundle { val port = new XilinxVC707PCIeX1IO - val slave_in = slave.bundleIn - val control_in = control.bundleIn - val master_out = master.bundleOut - val interrupt = intnode.bundleOut - } + }) io.port <> axi_to_pcie_x1.module.io.port diff --git a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index ac1c487..2fb476f 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -3,7 +3,7 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1 import Chisel._ import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) @@ -21,7 +21,7 @@ trait HasSystemXilinxVC707PCIeX1Bundle { } } -trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp +trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyModuleImp with HasSystemXilinxVC707PCIeX1Bundle { val outer: HasSystemXilinxVC707PCIeX1 val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO) diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index fe9221b..fac545a 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -219,27 +219,24 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule lazy val module = new LazyModuleImp(this) { // The master on the control port must be AXI-lite - require (control.edgesIn(0).master.endId == 1) + require (control.edges.in(0).master.endId == 1) // Must have exactly the right number of idBits - require (slave.edgesIn(0).bundle.idBits == 4) + require (slave.edges.in(0).bundle.idBits == 4) class VC707AXIToPCIeX1IOBundle extends Bundle with VC707AXIToPCIeX1IOSerial with VC707AXIToPCIeX1IOClocksReset; - val io = new Bundle { + val io = IO(new Bundle { val port = new VC707AXIToPCIeX1IOBundle - val slave_in = slave.bundleIn - val control_in = control.bundleIn - val master_out = master.bundleOut val REFCLK = Bool(INPUT) - val interrupt_out = intnode.bundleOut - } + }) val blackbox = Module(new vc707axi_to_pcie_x1) - val s = io.slave_in(0) - val c = io.control_in(0) - val m = io.master_out(0) + val (s, _) = slave.in(0) + val (c, _) = control.in(0) + val (m, _) = master.out(0) + val (i, _) = intnode.out(0) //to top level blackbox.io.axi_aresetn := io.port.axi_aresetn @@ -250,7 +247,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule io.port.pci_exp_txn := blackbox.io.pci_exp_txn blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn - io.interrupt_out(0)(0) := blackbox.io.interrupt_out + i(0) := blackbox.io.interrupt_out blackbox.io.REFCLK := io.REFCLK //s