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diplomacy: update to new API (#7)

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This commit is contained in:
Wesley W. Terpstra
2017-09-27 16:32:43 -07:00
committed by GitHub
parent 32d4083890
commit 4af0552374
5 changed files with 26 additions and 35 deletions
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16
src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
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@ -30,8 +30,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton")
val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
val axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = c.address,
resources = device.reg,
@ -48,8 +47,8 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
val yank = LazyModule(new AXI4UserYanker)
val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
val node: TLInwardNode = xing.node
toaxi4.node := xing.node
axi4 := buffer.node
buffer.node := yank.node
yank.node := deint.node
@ -57,10 +56,9 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val port = new XilinxVC707MIGIO(depth)
val tl = node.bundleIn
}
})
//MIG black box instantiation
val blackbox = Module(new vc707mig(depth))
@ -91,12 +89,12 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
val (axi_async, _) = axi4.in(0)
xing.module.io.in_clock := clock
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
(Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
Seq(toaxi4, indexer, deint, yank, buffer) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}

4
src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
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@ -4,7 +4,7 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707mig
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.HasMemoryBus
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange}
case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
@ -24,7 +24,7 @@ trait HasMemoryXilinxVC707MIGBundle {
}
}
trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
trait HasMemoryXilinxVC707MIGModuleImp extends LazyModuleImp
with HasMemoryXilinxVC707MIGBundle {
val outer: HasMemoryXilinxVC707MIG
val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)

16
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -21,10 +21,10 @@ class XilinxVC707PCIeX1IO extends Bundle
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLAsyncInputNode()
val control = TLAsyncInputNode()
val master = TLAsyncOutputNode()
val intnode = IntOutputNode()
val slave = TLAsyncIdentityNode()
val control = TLAsyncIdentityNode()
val master = TLAsyncIdentityNode()
val intnode = IntIdentityNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@ -56,13 +56,9 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val io = IO(new Bundle {
val port = new XilinxVC707PCIeX1IO
val slave_in = slave.bundleIn
val control_in = control.bundleIn
val master_out = master.bundleOut
val interrupt = intnode.bundleOut
}
})
io.port <> axi_to_pcie_x1.module.io.port

4
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -3,7 +3,7 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
import Chisel._
import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
@ -21,7 +21,7 @@ trait HasSystemXilinxVC707PCIeX1Bundle {
}
}
trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyModuleImp
with HasSystemXilinxVC707PCIeX1Bundle {
val outer: HasSystemXilinxVC707PCIeX1
val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)