riscv/fpga-shells
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Fixing typos in the tcl script

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This commit is contained in:
Shreesha Srinath 2017-08-18 11:34:35 -07:00
parent ae767458af
commit 38afe2957f
1 changed files with 2 additions and 2 deletions
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4
xilinx/common/tcl/vivado.tcl
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@ -5,7 +5,7 @@ source [file join $scriptdir "synth.tcl"]
# Pre-implementation debug # Pre-implementation debug
if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} { if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(PRE_IMPL_DEBUG_TCL)] source [file join $scriptdir $::env(PRE_IMPL_DEBUG_TCL)]
} }
# Post synthesis optimization # Post synthesis optimization
@ -22,7 +22,7 @@ source [file join $scriptdir "bitstream.tcl"]
# Post-implementation debug # Post-implementation debug
if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} { if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(POST_IMPL_DEBUG_TCL)] source [file join $scriptdir $::env(POST_IMPL_DEBUG_TCL)]
} }
# Create reports for the current implementation # Create reports for the current implementation