Move Xilinx unisims into separate file
This commit is contained in:
Henry Styles
Wesley W. Terpstra
parent
8b0d7ec91a
commit
33c88b8cc4
320
src/main/scala/ip/xilinx/Unisim.scala
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320
src/main/scala/ip/xilinx/Unisim.scala
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@ -0,0 +1,320 @@
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// See LICENSE for license details.
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package sifive.fpgashells.ip.xilinx
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import Chisel._
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import chisel3.{Input, Output}
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import chisel3.experimental.{Analog, attach, StringParam, RawParam, IntParam, DoubleParam}
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import sifive.blocks.devices.pinctrl.{BasePin}
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object booleanToVerilogVectorParam extends (Boolean => RawParam) {
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def apply(b : Boolean) : RawParam = if(b) RawParam("1") else RawParam("0")
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}
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object booleanToVerilogStringParam extends (Boolean => StringParam) {
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def apply(b : Boolean) : StringParam = if(b) StringParam("""TRUE""") else StringParam("""FALSE""")
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}
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/** IBUFDS -- SelectIO Differential Input */
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class IBUFDS(
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CAPACITANCE : String = "DONT_CARE",
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DIFF_TERM : Boolean = false,
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DQS_BIAS : Boolean = false,
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IBUF_DELAY_VALUE : Int = 0,
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IBUF_LOW_PWR : Boolean = true,
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IFD_DELAY_VALUE : String = "AUTO",
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IOSTANDARD : String = "DEFAULT"
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)
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extends BlackBox(
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Map(
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"CAPACITANCE" -> StringParam(CAPACITANCE),
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"DIFF_TERM" -> booleanToVerilogStringParam(DIFF_TERM),
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"DQS_BIAS" -> booleanToVerilogStringParam(DQS_BIAS),
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"IBUF_DELAY_VALUE" -> IntParam(IBUF_DELAY_VALUE),
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"IBUDF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR),
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"IFD_DELAY_VALUE" -> StringParam(IFD_DELAY_VALUE),
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"IOSTANDARD" -> StringParam(IOSTANDARD)
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)
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) {
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val io = IO(new Bundle {
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val O = Bool(OUTPUT)
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val I = Bool(INPUT)
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val IB = Bool(INPUT)
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})
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}
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/** IBUFG -- Clock Input Buffer */
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class IBUFG extends BlackBox {
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val io = IO(new Bundle {
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val O = Output(Clock())
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val I = Input(Clock())
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})
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}
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object IBUFG {
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def apply (pin: Clock): Clock = {
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val pad = Module (new IBUFG())
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pad.io.I := pin
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pad.io.O
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}
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}
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/** IBUFDS_GTE2 -- Differential Signaling Input Buffer */
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class IBUFDS_GTE2(
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CLKCM_CFG : Boolean = true,
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CLKRCV_TRST : Boolean = true,
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CLKSWING_CFG : Int = 3
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)
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extends BlackBox(
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Map(
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"CLKCM_CFG" -> booleanToVerilogStringParam(CLKCM_CFG),
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"CLKRCV_TRST" -> booleanToVerilogStringParam(CLKCM_CFG),
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"CLKSWING_CFG" -> IntParam(CLKSWING_CFG)
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)
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) {
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val io = IO(new Bundle {
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val O = Bool(OUTPUT)
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val ODIV2 = Bool(OUTPUT)
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val CEB = Bool(INPUT)
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val I = Bool(INPUT)
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val IB = Bool(INPUT)
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})
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}
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/** IDDR - 7 Series SelectIO DDR flop */
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class IDDR(
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DDR_CLK_EDGE : String = "OPPOSITE_EDGE",
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INIT_Q1 : Boolean = false,
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INIT_Q2 : Boolean = false,
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IS_C_INVERTED : Boolean = false,
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IS_D_INVERTED : Boolean = false,
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SRTYPE : String = "SYNC"
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)
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extends BlackBox(
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Map(
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"DDR_CLK_EDGE" -> StringParam(DDR_CLK_EDGE),
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"INIT_Q1" -> booleanToVerilogVectorParam(INIT_Q1),
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"INIT_Q2" -> booleanToVerilogVectorParam(INIT_Q2),
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"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
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"IS_D_INVERTED" -> booleanToVerilogVectorParam(IS_D_INVERTED),
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"SRTYPE" -> StringParam(SRTYPE)
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)
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) {
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val io = IO(new Bundle {
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val Q1 = Output(Bool())
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val Q2 = Output(Bool())
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val C = Input(Bool())
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val CE = Input(Bool())
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val D = Input(Bool())
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val R = Input(Bool())
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val S = Input(Bool())
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})
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}
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/** IDELAYCTRL - 7 Series SelectIO */
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class IDELAYCTRL(
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sim_device : String = "7SERIES"
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)
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extends BlackBox(
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Map(
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"SIM_DEVICE" -> StringParam(sim_device)
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)
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) {
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val io = IO(new Bundle {
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val RDY = Output(Bool())
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val REFCLK = Input(Bool())
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val RST = Input(Bool())
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})
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}
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/** IDELAYE2 -- 7 Series SelectIO ILogic programmable delay. */
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class IDELAYE2(
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CINVCTRL_SEL : Boolean = false,
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DELAY_SRC : String = "IDATAIN",
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HIGH_PERFORMANCE_MODE : Boolean = false,
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IDELAY_TYPE : String = "FIXED",
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IDELAY_VALUE : Int = 0,
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IS_C_INVERTED : Boolean = false,
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IS_DATAIN_INVERTED : Boolean = false,
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IS_IDATAIN_INVERTED : Boolean = false,
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PIPE_SEL : Boolean = false,
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REFCLK_FREQUENCY : Double = 200.0,
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SIGNAL_PATTERN : String = "DATA",
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SIM_DELAY_D : Int = 0
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)
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extends BlackBox(
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Map(
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"CINVCTRL_SEL" -> booleanToVerilogStringParam(CINVCTRL_SEL),
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"DELAY_SRC" -> StringParam(DELAY_SRC),
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"HIGH_PERFORMANCE_MODE" -> booleanToVerilogStringParam(HIGH_PERFORMANCE_MODE),
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"IDELAY_TYPE" -> StringParam(IDELAY_TYPE),
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"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
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"IS_DATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_DATAIN_INVERTED),
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"IS_IDATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_IDATAIN_INVERTED),
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"PIPE_SEL" -> booleanToVerilogStringParam(PIPE_SEL),
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"REFCLK_FREQUENCY" -> DoubleParam(REFCLK_FREQUENCY),
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"SIGNAL_PATTERN" -> StringParam(SIGNAL_PATTERN),
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"SIM_DELAY_D" -> IntParam(SIM_DELAY_D)
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)
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) {
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val io = IO(new Bundle {
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val DATAOUT = Output(Bool())
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val CNTVALUEOUT = Output(UInt(5.W))
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val C = Input(Bool())
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val CE = Input(Bool())
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val CINVCTRL = Input(Bool())
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val DATAIN = Input(Bool())
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val IDATAIN = Input(Bool())
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val INC = Input(Bool())
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val LD = Input(Bool())
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val LDPIPEEN = Input(Bool())
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val REGRST = Input(Bool())
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val CNTVALUEIN = Input(UInt(5.W))
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})
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}
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/** IOBUF -- Bidirectional IO Buffer. */
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//Cannot convert to BlackBox because of line
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//val IO = IO(Analog(1.W))
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//is illegal
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class IOBUF extends BlackBox {
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val io = new Bundle {
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val O = Output(Bool())
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val IO = Analog(1.W)
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val I = Input(Bool())
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val T = Input(Bool())
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}
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}
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object IOBUF {
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def apply (pin: Analog, ctrl: BasePin): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := ctrl.o.oval
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pad.io.T := ~ctrl.o.oe
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ctrl.i.ival := pad.io.O & ctrl.o.ie
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attach(pad.io.IO, pin)
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pad.io.O & ctrl.o.ie
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}
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// Creates an output IOBUF
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def apply (pin: Analog, in: Bool): Unit = {
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val pad = Module(new IOBUF())
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pad.io.I := in
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pad.io.T := false.B
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attach(pad.io.IO, pin)
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}
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// Creates an input IOBUF
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def apply (pin: Analog): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := false.B
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pad.io.T := true.B
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attach(pad.io.IO, pin)
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pad.io.O
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}
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}
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/** ODDR - 7 Series SelectIO DDR flop */
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class ODDR(
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DDR_CLK_EDGE : String = "OPPOSITE_EDGE",
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INIT : Boolean = false,
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IS_C_INVERTED : Boolean = false,
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IS_D1_INVERTED : Boolean = false,
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IS_D2_INVERTED : Boolean = false,
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SRTYPE : String = "SYNC"
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)
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extends BlackBox(
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Map(
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"DDR_CLK_EDGE" -> StringParam(DDR_CLK_EDGE),
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"INIT" -> booleanToVerilogVectorParam(INIT),
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"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
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"IS_D1_INVERTED" -> booleanToVerilogVectorParam(IS_D1_INVERTED),
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"IS_D2_INVERTED" -> booleanToVerilogVectorParam(IS_D2_INVERTED),
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"SRTYPE" -> StringParam(SRTYPE)
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)
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) {
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val io = IO(new Bundle {
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val Q = Output(Bool())
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val C = Input(Bool())
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val CE = Input(Bool())
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val D1 = Input(Bool())
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val D2 = Input(Bool())
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val R = Input(Bool())
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val S = Input(Bool())
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})
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}
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/** ODELAYE2 -- 7 Series SelectIO OLogic programmable delay. */
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class ODELAYE2(
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CINVCTRL_SEL : Boolean = false,
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DELAY_SRC : String = "ODATAIN",
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HIGH_PERFORMANCE_MODE : Boolean = false,
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IS_C_INVERTED : Boolean = false,
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IS_ODATAIN_INVERTED : Boolean = false,
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ODELAY_TYPE : String = "FIXED",
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ODELAY_VALUE : Int = 0,
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PIPE_SEL : Boolean = false,
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REFCLK_FREQUENCY : Double = 200.0,
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SIGNAL_PATTERN : String = "DATA",
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SIM_DELAY_D : Int = 0
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)
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extends BlackBox(
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Map(
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"CINVCTRL_SEL" -> booleanToVerilogStringParam(CINVCTRL_SEL),
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"DELAY_SRC" -> StringParam(DELAY_SRC),
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"HIGH_PERFORMANCE_MODE" -> booleanToVerilogStringParam(HIGH_PERFORMANCE_MODE),
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"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
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"IS_ODATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_ODATAIN_INVERTED),
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"ODELAY_TYPE" -> StringParam(ODELAY_TYPE),
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"PIPE_SEL" -> booleanToVerilogStringParam(PIPE_SEL),
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"REFCLK_FREQUENCY" -> DoubleParam(REFCLK_FREQUENCY),
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"SIGNAL_PATTERN" -> StringParam(SIGNAL_PATTERN),
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"SIM_DELAY_D" -> IntParam(SIM_DELAY_D)
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)
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) {
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val io = IO(new Bundle {
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val DATAOUT = Output(Bool())
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val CNTVALUEOUT = Output(UInt(5.W))
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val C = Input(Bool())
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val CE = Input(Bool())
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val CINVCTRL = Input(Bool())
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val CLKIN = Input(Bool())
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val INC = Input(Bool())
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val LD = Input(Bool())
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val LDPIPEEN = Input(Bool())
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val ODATAIN = Input(Bool())
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val REGRST = Input(Bool())
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val CNTVALUEIN = Input(UInt(5.W))
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})
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}
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/** PULLUP : can be applied to Input to add a Pullup. */
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class PULLUP extends BlackBox {
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val io = IO(new Bundle {
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val O = Analog(1.W)
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})
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}
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object PULLUP {
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def apply (pin: Analog): Unit = {
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val pullup = Module(new PULLUP())
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attach(pullup.io.O, pin)
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}
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}
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@ -13,99 +13,6 @@ import sifive.blocks.devices.pinctrl.{BasePin}
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// BlackBox modules used in the Xilinx FPGA flows
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//========================================================================
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//-------------------------------------------------------------------------
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// IBUFDS
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//-------------------------------------------------------------------------
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//IP : xilinx unisim IBUFDS. SelectIO Differential Signaling Input
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// Buffer unparameterized
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class IBUFDS extends BlackBox {
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val io = new Bundle {
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val O = Bool(OUTPUT)
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val I = Bool(INPUT)
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val IB = Bool(INPUT)
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}
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}
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//-------------------------------------------------------------------------
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// IBUFG
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//-------------------------------------------------------------------------
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/** IBUFG -- Clock Input Buffer */
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class IBUFG extends BlackBox {
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val io = new Bundle {
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val O = Output(Clock())
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val I = Input(Clock())
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}
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}
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object IBUFG {
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def apply (pin: Clock): Clock = {
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val pad = Module (new IBUFG())
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pad.io.I := pin
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pad.io.O
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}
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}
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//-------------------------------------------------------------------------
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// IOBUF
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//-------------------------------------------------------------------------
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/** IOBUF -- Bidirectional IO Buffer. */
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class IOBUF extends BlackBox {
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val io = new Bundle {
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val O = Output(Bool())
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val IO = Analog(1.W)
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val I = Input(Bool())
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val T = Input(Bool())
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}
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}
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object IOBUF {
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def apply (pin: Analog, ctrl: BasePin): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := ctrl.o.oval
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pad.io.T := ~ctrl.o.oe
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ctrl.i.ival := pad.io.O & ctrl.o.ie
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attach(pad.io.IO, pin)
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pad.io.O & ctrl.o.ie
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}
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// Creates an output IOBUF
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def apply (pin: Analog, in: Bool): Unit = {
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val pad = Module(new IOBUF())
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pad.io.I := in
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pad.io.T := false.B
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attach(pad.io.IO, pin)
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}
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// Creates an input IOBUF
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def apply (pin: Analog): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := false.B
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pad.io.T := true.B
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attach(pad.io.IO, pin)
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pad.io.O
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}
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}
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//-------------------------------------------------------------------------
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// PULLUP
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//-------------------------------------------------------------------------
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/** PULLUP : can be applied to Input to add a Pullup. */
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class PULLUP extends BlackBox {
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val io = new Bundle {
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val O = Analog(1.W)
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}
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}
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object PULLUP {
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def apply (pin: Analog): Unit = {
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val pullup = Module(new PULLUP())
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attach(pullup.io.O, pin)
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}
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}
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//-------------------------------------------------------------------------
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// mmcm
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Block a user