riscv/fpga-shells
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Merge remote-tracking branch 'origin/master' into synchronizers

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Megan Wachs 2017-09-07 10:46:03 -07:00
commit 31650a2d23
1 changed files with 4 additions and 4 deletions
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xilinx/vc707/constraints/vc707-master.xdc
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@ -40,11 +40,11 @@ set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp] create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5 set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}] set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}] set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}] set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}] set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
# JTAG # JTAG
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]