Fix the package path for xilinx vc707mig
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@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
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import sifive.fpgashells.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
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trait HasXilinxVC707MIGParameters {
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}
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