diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
index ab18860..127ed56 100644
--- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
+import sifive.fpgashells.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
 trait HasXilinxVC707MIGParameters {
 }