riscv/fpga-shells
1
0
Fork 0
Code Releases Activity

Fix the package path for xilinx vc707mig

Browse Source
This commit is contained in:
Shreesha Srinath
2017-08-18 14:47:03 -07:00
parent 38afe2957f
commit 2389e6e957
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
View File

@@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
import sifive.fpgashells.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
}