periphery: bus api update (#17)

* periphery: bus api update

* Update XilinxVC707MIGPeriphery.scala

src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala

@@ -5,7 +5,7 @@ import Chisel._
 import chisel3.experimental.{Analog,attach}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._

src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala

@@ -3,18 +3,18 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707mig
 
 import Chisel._
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex.HasMemoryBus
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange}
 
 case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
 
-trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+trait HasMemoryXilinxVC707MIG { this: BaseSubsystem =>
   val module: HasMemoryXilinxVC707MIGModuleImp
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey)))
 
-  require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
+  require(nMemoryChannels == 1, "Core complex must have 1 master memory port")
-  xilinxvc707mig.node := memBuses.head.toDRAMController
+  xilinxvc707mig.node := memBuses.head.toDRAMController(Some("xilinxvc707mig"))()
 }
 
 trait HasMemoryXilinxVC707MIGBundle {

src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala

@@ -3,12 +3,11 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
 
 import Chisel._
 import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.coreplex.CacheBlockBytes
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
-import freechips.rocketchip.coreplex.{HasCrossing,AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{HasCrossing, AsynchronousCrossing, CacheBlockBytes}
 import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
 import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
 

src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala

@@ -2,17 +2,17 @@
 package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
 
 import Chisel._
-import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.tilelink.{TLAsyncCrossingSource, TLAsyncCrossingSink}
 import freechips.rocketchip.interrupts.IntSyncCrossingSink
 
-trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
+trait HasSystemXilinxVC707PCIeX1 { this: BaseSubsystem =>
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-
+  private val name = Some("xilinxvc707pcie")
-  sbus.fromSyncFIFOMaster(BufferParams.none) := xilinxvc707pcie.crossTLOut := xilinxvc707pcie.master
+  sbus.fromMaster(name) { xilinxvc707pcie.crossTLOut } := xilinxvc707pcie.master
-  xilinxvc707pcie.slave := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
+  xilinxvc707pcie.slave := sbus.toFixedWidthSlave(name) { xilinxvc707pcie.crossTLIn }
-  xilinxvc707pcie.control := xilinxvc707pcie.crossTLIn := sbus.toFixedWidthSlaves
+  xilinxvc707pcie.control := sbus.toFixedWidthSlave(name) { xilinxvc707pcie.crossTLIn }
   ibus.fromSync := xilinxvc707pcie.crossIntOut := xilinxvc707pcie.intnode
 }