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periphery: bus api update (#17)

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* periphery: bus api update

* Update XilinxVC707MIGPeriphery.scala
This commit is contained in:
Henry Cook
2018-03-01 01:16:04 -08:00
committed by GitHub
parent 1dda525578
commit 0ca9f2bb66
4 changed files with 12 additions and 13 deletions
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3
src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -3,12 +3,11 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
import Chisel._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.coreplex.{HasCrossing,AsynchronousCrossing}
import freechips.rocketchip.subsystem.{HasCrossing, AsynchronousCrossing, CacheBlockBytes}
import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2