VC707 JTAG support throught XM105 FMC or reuse of LCD header
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@ -7,7 +7,7 @@ import chisel3.experimental.{RawModule, Analog, withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg}
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import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg, ElaborationArtefacts}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.spi._
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@ -222,7 +222,48 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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// Debug JTAG
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// Debug JTAG
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): SystemJTAGIO = {
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
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ElaborationArtefacts.add(
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"""debugjtag.vivado.tcl""",
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"""set vc707debugjtag_vivado_tcl_dir [file dirname [file normalize [info script]]]
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add_files -fileset [current_fileset -constrset] [glob -directory $vc707debugjtag_vivado_tcl_dir {*.vc707debugjtag.xdc}]"""
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)
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if(fmcxm105) {
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//VC707 constraints for Xilinx FMC XM105 Debug Card
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ElaborationArtefacts.add(
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"""vc707debugjtag.xdc""",
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"""set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
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)
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} else {
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//VC707 constraints for Olimex connect to LCD panel header
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ElaborationArtefacts.add(
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"""vc707debugjtag.xdc""",
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"""
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#Olimex Pin Olimex Function LCD Pin LCD Function FPGA Pin
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#1 VREF 14 5V
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#3 TTRST_N 1 LCD_DB7 AN40
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#5 TTDI 2 LCD_DB6 AR39
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#7 TTMS 3 LCD_DB5 AR38
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#9 TTCK 4 LCD_DB4 AT42
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#11 TRTCK NC NC NC
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#13 TTDO 9 LCD_E AT40
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#15 TSRST_N 10 LCD_RW AR42
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#2 VREF 14 5V
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#18 GND 13 GND
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN AT42 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN AR38 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN AR39 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN AT40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
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)
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}
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val djtag = dut.debug.systemjtag.get
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val djtag = dut.debug.systemjtag.get
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djtag.jtag.TCK := jtag_TCK
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djtag.jtag.TCK := jtag_TCK
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@ -64,13 +64,6 @@ set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}]
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set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
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set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
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set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]
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set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]
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# JTAG
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
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# SDIO
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# SDIO
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set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
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set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
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set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
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set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
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