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fpga-shells/xilinx/common/tcl/synth.tcl

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2017-08-16 20:23:45 +02:00
# See LICENSE for license details.
# Read the specified list of IP files
read_ip [glob -directory $ipdir [file join * {*.xci}]]
# Synthesize the design
synth_design -top $top -flatten_hierarchy rebuilt
# Checkpoint the current design
write_checkpoint -force [file join $wrkdir post_synth]