1
0
fpga-shells/xilinx/common/tcl/bitstream.tcl

11 lines
365 B
Tcl
Raw Normal View History

2017-08-16 20:23:45 +02:00
# See LICENSE for license details.
# Write a bitstream for the current design
write_bitstream -force [file join $wrkdir "${top}.bit"]
# Save the timing delays for cells in the design in SDF format
write_sdf -force [file join $wrkdir "${top}.sdf"]
# Export the current netlist in verilog format
write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]