2017-08-16 20:23:45 +02:00
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#---------------Physical Constraints-----------------
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set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
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set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
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set_property BOARD_PIN {reset} [get_ports reset]
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create_clock -name sys_diff_clk -period 5.0 [get_ports sys_diff_clock_clk_p]
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set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5
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set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led_0]
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set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led_1]
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set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led_2]
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set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led_3]
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set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led_4]
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set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led_5]
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set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led_6]
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set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led_7]
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set_property PACKAGE_PIN AU33 [get_ports uart_rx]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
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set_property IOB TRUE [get_ports uart_rx]
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set_property PACKAGE_PIN AT32 [get_ports uart_ctsn]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn]
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set_property IOB TRUE [get_ports uart_ctsn]
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set_property PACKAGE_PIN AU36 [get_ports uart_tx]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_tx]
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set_property IOB TRUE [get_ports uart_tx]
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set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
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set_property IOB TRUE [get_ports uart_rtsn]
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2017-08-18 03:51:01 +02:00
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# Platform specific constraints
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set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
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2017-09-07 18:54:35 +02:00
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set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"]
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2017-08-16 20:23:45 +02:00
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# PCI Express
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#FMC 1 refclk
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set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
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set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
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create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
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set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
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2017-09-07 19:41:12 +02:00
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set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
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set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
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2017-08-16 20:23:45 +02:00
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2017-09-07 19:41:12 +02:00
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set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
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set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
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2017-08-16 20:23:45 +02:00
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# JTAG
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
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# SDIO
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set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
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set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
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set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[0]}]
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set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
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set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
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set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
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set_clock_groups -asynchronous \
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-group { clk_pll_i } \
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-group { \
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clk_out1_vc707clk_wiz_sync \
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clk_out2_vc707clk_wiz_sync \
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clk_out3_vc707clk_wiz_sync \
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clk_out4_vc707clk_wiz_sync \
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clk_out5_vc707clk_wiz_sync \
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clk_out6_vc707clk_wiz_sync \
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clk_out7_vc707clk_wiz_sync } \
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-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]
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