Fixed timer.c and timer.h.
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4b4f451024
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5d550a0121
@ -31,10 +31,11 @@ void timer_reset(void)
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highBits64 = 0;
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}
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ISR(TIMER1_OVF_vect)
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// ISR(TIMER1_OVF_vect)
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void timer_overflow(void)
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{
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highBits32 += 0x01 00 00 00;
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highBits64 += 0x00 00 00 00 01 00 00 00;
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highBits32 += 0x01000000;
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highBits64 += 0x0000000001000000;
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}
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uint32_t timer_now32(void)
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@ -49,4 +50,4 @@ uint64_t timer_now64(void)
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uint64_t lowBits = TCNT0;
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uint64_t middleBits = TCNT1;
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return highBits64 | (middleBits<<8) | lowBits;
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}
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}
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@ -7,8 +7,9 @@
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void timer_init(void);
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void timer_reset(void);
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void timer_overflow(void);
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ISR(TIMER1_OVF_vect);
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// ISR(TIMER1_OVF_vect);
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uint32_t timer_now32(void);
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uint64_t timer_now64(void);
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@ -19,4 +20,4 @@ uint64_t timer_now64(void);
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uint32_t volatile highBits32; // max: ~214.7483648s
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uint64_t volatile highBits64; // max: ~29247a
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#endif
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#endif
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@ -19,7 +19,7 @@
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| TCCRnA_COMnB_toggle \
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| TCCRnA_COMnB_low \
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| TCCRnA_COMnB_high )
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#define TCCRnB_CSn_CLEAR ~ 0x07
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// Timer/CounterN Interrupt Mask Register
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#define TIMSKn_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSKn_ENABLE_INTERRUPT_on_overflow 0x01
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@ -120,4 +120,4 @@
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_B 0x04
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#endif
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#endif
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