Added timer.h/c, timer_macros.h.
Added tabs to cases b4 break in color_hsv.c
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4b4f451024
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@ -40,13 +40,12 @@ rgb_t hsv2rgb(hsv_t* hsv) {
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switch(h) {
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case 0:
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case 6: res.r = hsv->val; res.g = t; res.b = p; break;
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case 1: res.r = q; res.g = hsv->val; res.b = p; break;
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case 2: res.r = p; res.g = hsv->val; res.b = t; break;
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case 3: res.r = p; res.g = q; res.b = hsv->val; break;
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case 4: res.r = t; res.g = p; res.b = hsv->val; break;
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case 5: res.r = hsv->hue; res.g = p; res.b = q; break;
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case 6: res.r = hsv->val; res.g = t; res.b = p; break;
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case 1: res.r = q; res.g = hsv->val; res.b = p; break;
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case 2: res.r = p; res.g = hsv->val; res.b = t; break;
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case 3: res.r = p; res.g = q; res.b = hsv->val; break;
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case 4: res.r = t; res.g = p; res.b = hsv->val; break;
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case 5: res.r = hsv->hue; res.g = p; res.b = q; break;
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}
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}
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return res;
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@ -0,0 +1,52 @@
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#include "timer.h"
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#include "timer_macros.h"
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void timer_init(void)
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{
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//// Timer0
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// prescaler
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TCCR0B &= TCCRnB_CSn_CLEAR;
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TCCR0B |= TCCR0B_CS0_prescale1;
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// interrupt mask
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TIMSK0 &= TIMSKn_ENABLE_INTERRUPT_CLEAR;
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TIMSK0 |= TIMSK0_ENABLE_INTERRUPT_on_nothing;
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//// Timer1
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// prescaler
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TCCR1B &= TCCRnB_CSn_CLEAR;
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TCCR1B |= TCCR1B_CS1_prescale256;
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// interrupt mask
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TIMSK1 &= TIMSKn_ENABLE_INTERRUPT_CLEAR;
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TIMSK1 |= TIMSK1_ENABLE_INTERRUPT_on_overflow;
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SREG |= 0x80; // Status Register
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// Enable global interrupts
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}
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void timer_reset(void)
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{
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TCNT0 = 0;
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TCNT1 = 0;
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highBits32 = 0;
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highBits64 = 0;
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}
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ISR(TIMER1_OVF_vect)
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{
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highBits32 += 0x01 00 00 00;
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highBits64 += 0x00 00 00 00 01 00 00 00;
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}
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uint32_t timer_now32(void)
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{
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uint32_t lowBits = TCNT0;
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uint32_t middleBits = TCNT1;
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return highBits32 | (middleBits<<8) | lowBits;
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}
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uint64_t timer_now64(void)
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{
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uint64_t lowBits = TCNT0;
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uint64_t middleBits = TCNT1;
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return highBits64 | (middleBits<<8) | lowBits;
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}
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@ -0,0 +1,22 @@
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#ifndef _TIMER_H_
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#define _TIMER_H_
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <stdint.h>
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void timer_init(void);
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void timer_reset(void);
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ISR(TIMER1_OVF_vect);
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uint32_t timer_now32(void);
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uint64_t timer_now64(void);
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// counter | Timer1 | Timer0
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// 61(31)...24 | 23...8 | 7...0 <- Bits
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// 838.8608ms | 12.8µs | 50ns <- each lowest Bit represents
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uint32_t volatile highBits32; // max: ~214.7483648s
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uint64_t volatile highBits64; // max: ~29247a
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#endif
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@ -0,0 +1,123 @@
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#ifndef _AVR_MACROS_H_
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#define _AVR_MACROS_H_
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//// Compare Output Mode for Channel A
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#define TCCRnA_COMnA_disconnected 0x00
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#define TCCRnA_COMnA_toggle 0x40
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#define TCCRnA_COMnA_low 0x80
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#define TCCRnA_COMnA_high 0xf0
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#define TCCRnA_COMnA_CLEAR ~ ( TCCRnA_COMnA_disconnected \
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| TCCRnA_COMnA_toggle \
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| TCCRnA_COMnA_low \
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| TCCRnA_COMnA_high )
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// Compare Output Mode for Channel B
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#define TCCRnA_COMnB_disconnected 0x00
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#define TCCRnA_COMnB_toggle 0x10
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#define TCCRnA_COMnB_low 0x20
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#define TCCRnA_COMnB_high 0x30
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#define TCCRnA_COMnB_CLEAR ~ ( TCCRnA_COMnB_disconnected \
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| TCCRnA_COMnB_toggle \
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| TCCRnA_COMnB_low \
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| TCCRnA_COMnB_high )
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// Timer/CounterN Interrupt Mask Register
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#define TIMSKn_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSKn_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_B 0x04
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#define TIMSKn_ENABLE_INTERRUPT_CLEAR ~ ( TIMSKn_ENABLE_INTERRUPT_on_nothing \
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| TIMSKn_ENABLE_INTERRUPT_on_overflow \
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| TIMSKn_ENABLE_INTERRUPT_on_compare_match_A \
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| TIMSKn_ENABLE_INTERRUPT_on_compare_match_B )
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/**********************************************************/
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// Timer/Counter0 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR0A_COM0A_disconnected 0x00
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#define TCCR0A_COM0A_toggle 0x40
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#define TCCR0A_COM0A_low 0x80
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#define TCCR0A_COM0A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR0A_COM0B_disconnected 0x00
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#define TCCR0A_COM0B_toggle 0x10
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#define TCCR0A_COM0B_low 0x20
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#define TCCR0A_COM0B_high 0x30
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// Timer/Counter0 Control Register B
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// Clock Select 0 (prescaler)
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#define TCCR0B_CS0_stopped 0x00
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#define TCCR0B_CS0_prescale1 0x01
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#define TCCR0B_CS0_prescale8 0x02
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#define TCCR0B_CS0_prescale64 0x03
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#define TCCR0B_CS0_prescale256 0x04
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#define TCCR0B_CS0_prescale1024 0x05
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#define TCCR0B_CS0_falling_on_T0 0x06
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#define TCCR0B_CS0_rising_on_T0 0x07
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// Timer/Counter0 Interrupt Mask Register
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#define TIMSK0_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK0_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_B 0x04
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// Timer/Counter1 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR1A_COM1A_disconnected 0x00
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#define TCCR1A_COM1A_toggle 0x40
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#define TCCR1A_COM1A_low 0x80
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#define TCCR1A_COM1A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR1A_COM1B_disconnected 0x00
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#define TCCR1A_COM1B_toggle 0x10
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#define TCCR1A_COM1B_low 0x20
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#define TCCR1A_COM1B_high 0x30
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// Timer/Counter1 Control Register B
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// Clock Select 1 (prescaler)
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#define TCCR1B_CS1_stopped 0x00
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#define TCCR1B_CS1_prescale1 0x01
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#define TCCR1B_CS1_prescale8 0x02
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#define TCCR1B_CS1_prescale64 0x03
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#define TCCR1B_CS1_prescale256 0x04
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#define TCCR1B_CS1_prescale1024 0x05
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#define TCCR1B_CS1_falling_on_T1 0x06
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#define TCCR1B_CS1_rising_on_T1 0x07
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// Timer/Counter1 Interrupt Mask Register
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#define TIMSK1_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK1_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_B 0x04
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// Timer/Counter2 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR2A_COM2A_disconnected 0x00
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#define TCCR2A_COM2A_toggle 0x40
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#define TCCR2A_COM2A_low 0x80
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#define TCCR2A_COM2A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR2A_COM2B_disconnected 0x00
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#define TCCR2A_COM2B_toggle 0x10
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#define TCCR2A_COM2B_low 0x20
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#define TCCR2A_COM2B_high 0x30
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// Timer/Counter1 Control Register B
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// Clock Select 1 (prescaler)
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#define TCCR2B_CS2_stopped 0x00
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#define TCCR2B_CS2_prescale1 0x01
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#define TCCR2B_CS2_prescale8 0x02
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#define TCCR2B_CS2_prescale32 0x03
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#define TCCR2B_CS2_prescale64 0x04
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#define TCCR2B_CS2_prescale128 0x05
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#define TCCR2B_CS2_prescale256 0x06
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#define TCCR2B_CS2_prescale1024 0x07
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// Timer/Counter1 Interrupt Mask Register
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#define TIMSK2_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK2_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_B 0x04
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#endif
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