31 lines
659 B
VHDL
31 lines
659 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.ALL;
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entity adder is
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generic (
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WIDTH: integer
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);
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port (
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x: in std_logic_vector(WIDTH-1 downto 0);
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y: in std_logic_vector(WIDTH-1 downto 0);
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cin: in std_logic;
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sum: out std_logic_vector(WIDTH-1 downto 0);
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cout: out std_logic
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);
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end adder;
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architecture rtl of adder is
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signal result: unsigned(WIDTH downto 0);
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begin
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result <= resize(unsigned(x), WIDTH+1) +
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resize(unsigned(y), WIDTH+1) +
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("" & cin);
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sum <= std_logic_vector(result(WIDTH-1 downto 0));
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cout <= result(WIDTH);
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end rtl;
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