toy/computer
2
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Ad test bench for the computer control logic

Browse Source
This commit is contained in:
Klemens Schölhorn 2018-05-31 22:31:15 +02:00
parent 611e0ac388
commit e1a3ab745c
2 changed files with 165 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
firmware/alu/alu.xise
View File

@ -24,9 +24,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="tests/toy_16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="tests/control_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
@ -82,9 +86,9 @@
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="tests/control_logic.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -136,10 +140,10 @@
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="control_logic_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="control_logic_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="control_logic_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="control_logic_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@ -158,8 +162,8 @@
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/toy_16" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -173,7 +177,7 @@
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -213,7 +217,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|toy_16|test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

149
firmware/alu/tests/control_logic.vhd Normal file
View File

@ -0,0 +1,149 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control_logic is
end control_logic;
architecture test of control_logic is
component main
generic (
FIRST: boolean
);
port (
func: in std_logic_vector(3 downto 0);
accu: in std_logic_vector(7 downto 0);
ram: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
result: out std_logic_vector(7 downto 0);
carry_out: out std_logic
);
end component;
type ram_type is array(0 to 4095) of std_logic_vector(15 downto 0);
signal clk: std_logic;
signal first: boolean := false;
signal acc: std_logic_vector(15 downto 0) := (others => '0');
signal ir: std_logic_vector(15 downto 0) := (others => '0');
signal ram: ram_type := (
0 => "0001000000001010",
1 => "0011000000001000",
2 => "0000000000001010",
3 => "1011000000000000",
4 => "0010000000000000",
5 => "0000000000000000",
6 => "0000000000000101",
7 => "0000000000000111",
8 => "0001001110001000",
9 => "0000000000000000",
10 => "0000000000000000",
others => (others => '0')
);
signal pc: std_logic_vector(11 downto 0) := (others => '0');
signal data_out: std_logic_vector(15 downto 0);
signal data_in: std_logic_vector(15 downto 0);
signal carry_propagation: std_logic;
signal addr: std_logic_vector(11 downto 0);
signal op: std_logic_vector(3 downto 0);
signal write_ram: std_logic;
signal write_pc: std_logic;
signal inc_pc: std_logic;
signal ram_addr_ir: std_logic;
signal write_ir: std_logic;
signal write_acc: std_logic;
begin
op <= ir(15 downto 12);
addr <= ir(11 downto 0) when ram_addr_ir = '1' else pc;
data_out <= ram(to_integer(unsigned(addr)));
alu1: main generic map (
FIRST => true
) port map (
func => op,
accu => acc(7 downto 0),
ram => data_out(7 downto 0),
carry_in => '0',
result => data_in(7 downto 0),
carry_out => carry_propagation
);
alu2: main generic map (
FIRST => false
) port map (
func => op,
accu => acc(15 downto 8),
ram => data_out(15 downto 8),
carry_in => carry_propagation,
result => data_in(15 downto 8),
carry_out => open
);
process(clk)
begin
if rising_edge(clk) then
if write_acc = '1' then
acc <= data_in;
end if;
if write_ir = '1' then
ir <= data_out;
end if;
if write_ram = '1' then
ram(to_integer(unsigned(addr))) <= data_in;
end if;
if write_pc = '1' then
pc <= ir(11 downto 0);
elsif inc_pc = '1' then
pc <= std_logic_vector(unsigned(pc) + 1);
end if;
end if;
end process;
process(first, op, acc)
begin
write_ram <= '0';
write_pc <= '0';
inc_pc <= '0';
ram_addr_ir <= '1';
write_ir <= '0';
write_acc <= '1';
if first then
if op = "0000" then
write_ram <= '1';
end if;
if acc = "0000000000000000" and op = "0010" then
write_pc <= '1';
end if;
if op = "0000" or op = "0010" or op(3 downto 2) = "11" then
write_acc <= '0';
end if;
else
inc_pc <= '1';
ram_addr_ir <= '0';
write_ir <= '1';
write_acc <= '0';
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
first <= not first;
end if;
end process;
process
begin
clk <= '1';
wait for 1us;
clk <= '0';
wait for 1us;
end process;
end test;